Test: Number Systems, Boolean Algebra & Sequential Logic Circuits - Electronics and Communication Engineering (ECE) MCQ

In general, since we are comfortable dealing with Decimal system, the best way to go about under the circumstances is to convert one Number into decimal Number and then with the base x, convert another Number into Decimal Number and equate them to find the value of x.

So, (152)8 is 64*1+8*5+2, which is 106 in Decimal System.

(211)x is 2x^2+ 1*x+1 in Decimal System.

Now, we solve 2x^2+x+1 = 106

i. e. 2x^2+x-105=0

Therefore 2x^2–14x+15x-105=0

Therefore 2x(x-7)+15(x-7)=0

Therefore (x-7)(2x+15)=0

Therefore either x = 7 or x = -15/2.

Obviously x = -15/2 isnot the answer. So, x = 7 is the answer, which can be very easily verified. 2*7^2+1*7+1 = 106 which issame as (152)8.

Thus the base for 211 is 7.

All are 2’s complement of 7

See a example

From table it is clear that it is a MOD–3 counter.

It is a down counter because 0 state of previous FFs change the state of next FF. You may trace the following sequence, let initial state be000

It is a down counter because the inverted FF output drive the clock inputs. The NAND gate will clear FFs A and B when the count tries to recycle to 111. This will produce as result of 100. Thus the counting sequence will be 100, 011, 010, 001, 000, 100 etc.

It is a 5 bit ripple counter. At 11000 the output of NAND gate is LOW. This will clear all FF. So it is a Mod 24 counter. Note that when 11000 occur, the CLR input is activated and all FF are immediately cleared. So it is a MOD 24 counter not MOD 25.

10-bit ring counter is a MOD–10, so it divides the 160 kHz input by 10. therefore, w = 16 kHz. The four-bit parallel counter is a MOD–16. Thus, the frequency at x = 1 kHz. The MOD–25 ripple counter produces a frequency at y = 40 Hz. (1 kHz/25 = 40 Hz).
The four-bit Johnson Counter is a MOD-8. This, the frequency at z = 5 Hz.

We see that 1 0 1 repeat after every two cycles, hence frequency will be f_c/2 

At first cycle

In ripple counter delay 4T_d = 40 ns.

The synchronous counter are clocked simultaneously, then its worst delay will be equal to 10 ns.

4 bit uses 4 FF

On multiplying the decimal number continuously by 2, the binary equivalent is obtained.

X = [(A + B̅) (B + C)] B

= (AB + AC + 0 +  B̅C)B

= AB + ABC

= AB(1 + C)

= AB