Test: Pipelining Hazards - Computer Science Engineering (CSE) MCQ

∴ 2 true dependencies are there.
∴ f = 2GHz


Total cycles require = 11
∴ Execution time = 11 × 0.5 = 5.5 ns.

Concept:
Branch hazards occur when the pipeline makes wrong decisions on branch prediction and therefore brings instructions into the pipeline that must subsequently be discarded.

• The term branch hazard also refers to a control hazard or instruction hazard.
• Branch hazard form of dependence happens when control instructions such as BRANCH, CALL, JMP, and others are transferred. When the processor wants to introduce a new instruction into the pipeline, it will not know the target address of these instructions on many instruction architectures.

Hence the correct answer is Branch hazard.

Concept:
Hazards are the conditions that can prevent some instructions in the instruction stream from executing during its designated clock cycle.
Pipeline hazard is a condition that causes a stall in pipeline operations and degrades the performance of the pipeline. 
There are three types of pipeline hazard:

1. Control hazard: Control hazards occur due to wrong branch predictions and other instruction that causes changes in the program counter.
2. Data hazard: Data hazards occur when data dependency exists among instructions that are in different stages of execution in the pipeline.
3. Structural hazard: Structural hazard arises due to resource conflicts.

Hence, the Address hazard is NOT an instruction pipeline hazard.

The locality of the reference concept will fail where there are many unconditional jumps.
Concept
The locality of Reference: 

• It is the phenomenon in which a computer program tends to access the same set of memory locations for a particular time period. There are two basic types of reference locality – temporal and spatial locality.
• Temporal locality: If at one point a particular memory location is referenced, then it is likely that the same location will be referenced again in the near future.
• Spatial locality: If a particular storage location is referenced at a particular time, then it is likely that nearby memory locations will be referenced in the near future.
• In unconditional Jump, the computer program won't be able to access the same set of memory locations for a particular time period.

Initially A = 20

Instruction: X – 1, writes the value 70
Instruction: X, overwrites it with 90
In system, after T₁ and T₂ execution value of A = 90
Ideally value should be 20 + 50 + 70 = 140
These hazards arise due to write after write

Concept:
The given data,
Cycle time (tp) = 2 GHz = 0.5 nanoseconds.
K = 5,
X1:
Without branch prediction.

CPI = 1 + Number of stalls instruction
CPI = 1 + (0.3) × 2
CPI = 1.6
Average serial instruction execution time = CPI * Cycle time
Average serial instruction execution time = 1.6* 0.5nsec 
Average serial instruction execution time = 0.8 ns.
X2:
If BPU predicted the correct branch then it eliminate stalls but if BPU predicted the wrong branch then BPU does not add any additional stalls but the remaining stalls will be present.

CPI = 1+(0.3 ×0.2 ×2)
CPI =1.12
Average parallel instruction execution time = CPI × Cycle time
Average parallel instruction execution time = 1.12 × 0.5 ns
Average parallel instruction execution time = 0.56 ns.

Speedup:
A speedup is a number that measures the relative performance of two systems processing the same problem.
Speedup = Serial Execution Time / Parallel Execution Time.
Speed up= 0.8 / 0.56
Speed up=1.428
Hence the correct answer is 1.428.

Concept:
Resource conflicts caused by access to memory by two segments at the same time. Most of these conflicts can be resolved by using separate instructions and data memories.
Data dependency conflicts arise when an instruction depends on the result of a previous instruction, but this result is not yet available.

Option 1: True dependency
True dependency is when Read-after-Write or RAW occurs
Option 2: Anti-dependency
Anti-dependency is when Write-after-Read or WAR occurs
Option 3: Output Dependency
Output dependency is when Write-after-Write or WAW occurs
Option 4: Control hazard
Control Hazard is when pipeline makes wrong decisions on branch prediction

• Instruction set is said to be orthogonal if any instruction can use data of any type through any addressing mode.
• Orthogonality in other sense is,   instruction type and the addressing mode vary independently
• Orthogonality doesn’t limit any instruction to use specific register

• In the case of the delayed load technique, the compiler detects the data conflict and recorder the instruction as necessary to delay the loading of the conflicting data by inserting no operation instructions (NOP).
• Therefore the method used for resolving data dependency conflict by the compiler itself is delayed load.