Test: Sample & Hold Circuits - Electrical Engineering (EE) MCQ

Sample and Hold (S/H) circuit:

It is used with an analog to digital converter to sample the input analog signal and hold the sample signal.

Circuit:- 

Properties:
1. A S/H Circuit should have high input impedance and low output impedance because due to high input impedance loading effect [It is the degree to which a measurement instrument impact electrical properties (Voltage, Current, resistance) of a Circuit] is less and Circuit performance is better.

Conclusions:
for better circuit performance input impedance should be high and output impedance should be low.

Option 4 correct choice.

Zero-order hold circuit:

It is a mathematical model of two practical signal Reconstruction done by convention Digital to Analog converter (DAC).
By holding each sample value for one sample interval it converts the discrete signal into an analog signal.

Important Points

Zero-order function 

Sample & Hold Circuit is used to sample the given input signal and to hold the sampled value.
Sample and hold circuit is used to sample an analog signal for a short interval of time in the range of 1 to 10 µS and to hold on to its last sampled value, until the input signal is sampled again.
The holding period may be from a few milliseconds to several seconds.

Applications of Sample & Hold circuits:

• Out of different ADCs, successive approximation type ADC uses an S/H circuit, where the signal is to be held constant while A to D conversion is taking place.
• They are also used in DACs for the same purpose.
• It is used in analog demultiplexing in data distribution and in analog delay lines.
• In general, S/H circuits are used in all applications where it is necessary to stabilize the analog signal for further processing.

Concepts:

Generally, a sample & hold circuit is designed using an opamp. The given circuit shows the general implementation:

Sample & Hold circuit capacitor C_H is charged by the Amplifier A₁.
The maximum output current of the opamp is given as:

 
Droop rate  when V₀ is the voltage at the steady state.
The acquisition time (t_ac) is depicted in the following figure:

Analylsis:

 

If C­_H increases then ‘t’ which is the acquiring time must also increase to maintain the relationship.
Also, capacitor discharging time constant T_C(discharge) is proportional to capacitance i.e.

So if C_H increases then capacitor voltage decreases slowly because of discharging time constant, this means droop rate decreases.

Data Hold
Data hold is a process of generating a continuous-time signal h(t) from a discrete-time sequence x(kT).
The signal h(t) during the time interval kT ≤ t ≤ (k + 1)T may be approximated by a polynomial in τ as follows:
h(kT + τ ) = a_nτⁿ + a_n−1τⁿ⁻¹ + ··· + a₁τ + a₀
Where 0 ≤ τ ≤ T

Note: h(kT) = x(kT)
h(kT + τ ) = a_nτⁿ + a_n−1τⁿ⁻¹ + ··· + a₁τ + x(kT)
If the data hold circuit is an n^th-order polynomial extrapolator, it is called an n^th-order hold. It uses the past n + 1 discrete data x((k − n)T), x((k − n + 1)T), ··· , x(kT) to generate h(kT + τ ).

Conclusion:
As the order of the data hold increases the circuit order(n) also increases which leads to the further increase in the time delay because it has to use past n + 1 samples.
Option 3 is correct.

In an ADC along with sample and hold circuit, for avoiding error at the output, the voltage of the capacitor should be not dropped by more than ± Δ/2

Δ/2 = 4.88 × 10³ V
Maximum conversation time for the ADC is

= 48.87 msec ≈ 49 msec

Sample and Hold circuit:
It samples the incoming analog signal and holds this sample values for a certain instant of time.
In the basic circuit diagram, an analog switch and a capacitor is used to perform the work.

In this circuit, the switch can be either BJT, MOSFET, etc.
When the switch is closed by the applied input signal, the capacitor starts charging and holds the sampled value and the sampling interval is the same as the charging duration of the capacitor.
The capacitor holds the sampled value for half interval and changes its value in another half interval of time.

Application of sample and hold circuit

Analog to digital converter

• Signal processing
• Filter design
• Oscilloscope

Explanation:
When a time varying signal has to be digitized using an ADC, sample and hold circuit is necessary to use before digitation. Because sample and hold circuit take sample at particular instant.

The electronic device that performs this conversion from an analog signal to a digital sequence is called an analog-to-digital (A/D) converter (ADC).

The A/D converter begins the conversion after it receives a convert command. The time required to complete the conversion should be less than the duration of the hold mode of S/H.

The A/D converter begins the conversion after it receives a convert command. The sampling period T should be larger than the duration of the sample mode and the hold mode.