Which of the following is a type of hazard that occurs due to resource conflicts in a pipeline? A) Data hazard B) Control hazard C) Resource hazard D) Structural hazard

C) Resource hazard

Riddle: I help fetch the next instruction while the current one is executed, but my effectiveness can be hindered by branches. What am I?

Instruction prefetch

True or False: The fetch and execute stages of a pipeline are always equal in duration, allowing for ideal speedup.

False. The execution time is generally longer than the fetch time, causing potential delays.

Fill-in-the-blanks: A pipeline must have more stages to gain further speedup, which includes stages such as Fetch instruction (FI), ______, and Execute instruction (EI).

Decode instruction (DI)

What is the main purpose of a loop buffer in pipelining?

To store the most recently fetched instructions and reduce the latency of branch target fetching.

Which of the following is a characteristic of Reduced Instruction Set Computers (RISC)? A) Complex addressing modes B) Variable-length instruction formats C) Single-cycle instruction execution D) Large number of instructions

C) Single-cycle instruction execution

Fill-in-the-blanks: A pipeline stall due to conditions not permitting continued execution is referred to as a ______.

Pipeline bubble

True or False: Control hazards occur when the pipeline fetches instructions that must be executed in sequence without any branching.

False. Control hazards occur when the pipeline makes incorrect predictions about branch instructions.

Riddle: I’m a set of processors working in parallel, handling multiple data with a single instruction. What am I?

SIMD array processor

What is the primary function of the EFLAGS register in the x86 architecture?

To indicate the condition of the processor and control its operation through various status flags.