Analog Circuits Formulas for GATE ECE Exam | Analog Circuits - Electronics and Communication Engineering (ECE) PDF Download

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 Page 1


• Energy gap
???? G/si
=1.21- 3.6 × 10
-4
.T   ev
???? G/Ge
=0.785- 2.23 × 10
-4
.T   ev
? Energy gap depending on temperature 
• E
F
 = E
C
 - KT ln?
???? ???? ???? ???? ? = E
v
 + KT ln ?
???? ???? ???? ???? ? 
• No. of electrons  n = N
c
 e
-(E
c
-E
f
)/RT
         (KT in ev) 
• No. of holes  p = N
v
 e
-(E
f
-E
v
)/RT
• Mass action law  n
p
 = n
i
2
 = N
c
N
v
 e
-EG/KT
• Drift velocity  ???? d
 = µE  (for si ???? d
 = 10
7
 cm/sec)
• Hall voltage ???? H
 = 
B.I
w
e
 . Hall coefficient  R
H
 = 1/? .            ? ? charge density = qN
0
 = ne … 
• Conductivity  s = ?µ ;  µ = sR
H
 .
• Max value of electric field @ junction E
0
 =  -
q
?
si
N
d
. n
n0
 =  -
q
?
si
 N
A
. n
p0
 . 
• Charge storage @ junction  Q
+
 = - Q
-
 = qA x
n0
N
D
 =  qA x
p0
N
A
• Diffusion current densities  J
p
 = - q D
p
 
dp
dx
J
n
 = - q D
n
 
dn
dx
• Drift current Densities  = q(p µ
p
+ nµ
n
)E
• µ
p
 , µ
n
 decrease with increasing doping concentration .
•
D
n
µ
n
= 
D
p
µ
p
 = KT/q ˜ 25 mv @ 300 K 
• Carrier concentration in N-type silicon n
n0
 = N
D
 ;  p
n0
 = n
i
2
 / N
D
• Carrier concentration in P-type silicon p
p0
 = N
A
 ;  n
p0
 = n
i
2
 / N
A
• Junction built in voltage  V
0
 = V
T
 ln ?
???? ???? ???? ???? ???? ???? 2
? 
• Width of Depletion region  W
dep
 =  x
p
 + x
n
 = ?
2e
s
q
?
1
N
A
+
1
N
D
?(V
0
+ V
R
) 
* ?
2???? ???????? ???? = 12.93???? ???????????? ???????? ?  
•
x
n
x
p
 = 
N
A
N
D
 
• Charge stored in depletion region  q
J
 = 
q.N
A
 N
D
N
A
+N
D
 . A . W
dep
  
• Depletion capacitance  C
j
 = 
e
s
A
W
dep
 ;   C
j0
 = 
e
s
A
W
dep
/ V
R
=0
C
j
 = C
j0
/? 1 +
V
R
V
0
?
m
  C
j
 = 2C
j0
  (for forward Bias) 
• Forward current  I = I
p
+ I
n
 ;       I
p
 = Aq n
i
2
D
p
L
p
N
D
 ? ???? ???? /???? ???? - 1? 
I
n
 = Aq n
i
2
 
D
n
L
n
N
A
 ? ???? ???? /???? ???? - 1?  
• Saturation Current  I
s
 = Aq n
i
2
  ?
D
p
L
p
N
D
+
D
n
L
n
N
A
? 
• Minority carrier life time  t
p
 = L
p
2
 / D
p
  ;    t
n
 = L
n
2
 / D
n
Analog Circuits (Formula Notes/Short Notes)
Page 2


• Energy gap
???? G/si
=1.21- 3.6 × 10
-4
.T   ev
???? G/Ge
=0.785- 2.23 × 10
-4
.T   ev
? Energy gap depending on temperature 
• E
F
 = E
C
 - KT ln?
???? ???? ???? ???? ? = E
v
 + KT ln ?
???? ???? ???? ???? ? 
• No. of electrons  n = N
c
 e
-(E
c
-E
f
)/RT
         (KT in ev) 
• No. of holes  p = N
v
 e
-(E
f
-E
v
)/RT
• Mass action law  n
p
 = n
i
2
 = N
c
N
v
 e
-EG/KT
• Drift velocity  ???? d
 = µE  (for si ???? d
 = 10
7
 cm/sec)
• Hall voltage ???? H
 = 
B.I
w
e
 . Hall coefficient  R
H
 = 1/? .            ? ? charge density = qN
0
 = ne … 
• Conductivity  s = ?µ ;  µ = sR
H
 .
• Max value of electric field @ junction E
0
 =  -
q
?
si
N
d
. n
n0
 =  -
q
?
si
 N
A
. n
p0
 . 
• Charge storage @ junction  Q
+
 = - Q
-
 = qA x
n0
N
D
 =  qA x
p0
N
A
• Diffusion current densities  J
p
 = - q D
p
 
dp
dx
J
n
 = - q D
n
 
dn
dx
• Drift current Densities  = q(p µ
p
+ nµ
n
)E
• µ
p
 , µ
n
 decrease with increasing doping concentration .
•
D
n
µ
n
= 
D
p
µ
p
 = KT/q ˜ 25 mv @ 300 K 
• Carrier concentration in N-type silicon n
n0
 = N
D
 ;  p
n0
 = n
i
2
 / N
D
• Carrier concentration in P-type silicon p
p0
 = N
A
 ;  n
p0
 = n
i
2
 / N
A
• Junction built in voltage  V
0
 = V
T
 ln ?
???? ???? ???? ???? ???? ???? 2
? 
• Width of Depletion region  W
dep
 =  x
p
 + x
n
 = ?
2e
s
q
?
1
N
A
+
1
N
D
?(V
0
+ V
R
) 
* ?
2???? ???????? ???? = 12.93???? ???????????? ???????? ?  
•
x
n
x
p
 = 
N
A
N
D
 
• Charge stored in depletion region  q
J
 = 
q.N
A
 N
D
N
A
+N
D
 . A . W
dep
  
• Depletion capacitance  C
j
 = 
e
s
A
W
dep
 ;   C
j0
 = 
e
s
A
W
dep
/ V
R
=0
C
j
 = C
j0
/? 1 +
V
R
V
0
?
m
  C
j
 = 2C
j0
  (for forward Bias) 
• Forward current  I = I
p
+ I
n
 ;       I
p
 = Aq n
i
2
D
p
L
p
N
D
 ? ???? ???? /???? ???? - 1? 
I
n
 = Aq n
i
2
 
D
n
L
n
N
A
 ? ???? ???? /???? ???? - 1?  
• Saturation Current  I
s
 = Aq n
i
2
  ?
D
p
L
p
N
D
+
D
n
L
n
N
A
? 
• Minority carrier life time  t
p
 = L
p
2
 / D
p
  ;    t
n
 = L
n
2
 / D
n
Analog Circuits (Formula Notes/Short Notes)
• Minority carrier charge storage  Q
p
 = t
p
I
p
 ,  Q
n
 = t
p
I
n
     Q = Q
p
 + Q
n
 = t
T
I              t
T
 = mean transist time 
• Diffusion capacitance  C
d
 =  ?
???? ???? ???????? ???? ? I = t.g  ? C
d
 ? I. 
t? carrier life time ,  g = conductance = I /  ???????? ????  
• I
02
 = 2
(T
2
-T
1
)/10
 I
01
• Junction Barrier Voltage  V
j
 = V
B
 = V
r
 (open condition)
           = V
r
 - V (forward Bias) 
           =  V
r
 + V (Reverse Bias) 
• Probability of filled states above ‘E’  f(E) = 
1
1+e
(E-E
f
)/KT
  
• Drift velocity of  e
-
        ???? d
 = 10
7
 cm/sec 
• Poisson equation  
d
2
V
dx
2
 = 
-?
v
?
  = 
-nq
?
 ? 
dv
dx
 = E = 
-nqx
?
  
Transistor :- 
• I
E
 = I
DE
 + I
nE
• I
C
 = I
Co
 – a I
E
  ? Active region
• I
C
 = – a I
E
 + I
Co
 (1- e
V
C
/V
T
 )
Common Emitter :- 
• I
C
 = (1+ ß) I
Co
 + ßI
B
    ß = 
a
1-a
• I
CEO
 = 
I
Co
1-a
  ? Collector current when base open 
• I
CBO
 ? Collector current when I
E
 = 0        I
CBO
 > I
Co
 .
• V
BE,sat
  or  V
BC,sat
 ?  - 2.5 mv /
0
 C ;    V
CE,sat
 ? 
V
BE,sat
10
 = - 0.25 mv /
0
C 
• Large signal Current gain  ß =  
I
C
- I
CBo
I
B
+ I
CBo
• D.C current gain  ß
dc
 = 
I
C
I
B
 = h
FE
  
• (ß
dc
 = h
FE
 ) ˜ ß   when  I
B
 > I
CBo
• Small signal current gain ß
'
 = 
?I
C
?I
R
?
V
CE
 =  h
fe
 =  
h
FE
1-(I
CBo
+ I
B
)
?h
FE
?I
C
  
• Over drive factor =
ß
active
ß
forced
?under saturation
 ? I
C sat
 = ß
forced
 I
B sat
   
Conversion formula :- 
   CC  ? CE 
• h
ic
 = h
ie
 ;     h
rc
 = 1 ;         h
fc
 = - (1+ h
fe
) ;      h
oc
 = h
oe
 
 CB  ? CE 
• h
ib
 = 
h
ie
1+h
fe
;  h
ib
 = 
h
ie
 h
oe
1+h
fe
- h
re
 ; h
fb
 = 
-h
fe
1+h
fe
;    h
ob
 = 
h
oe
1+h
fe
CE parameters in terms of CB can be obtained by interchanging B & E . 
Page 3


• Energy gap
???? G/si
=1.21- 3.6 × 10
-4
.T   ev
???? G/Ge
=0.785- 2.23 × 10
-4
.T   ev
? Energy gap depending on temperature 
• E
F
 = E
C
 - KT ln?
???? ???? ???? ???? ? = E
v
 + KT ln ?
???? ???? ???? ???? ? 
• No. of electrons  n = N
c
 e
-(E
c
-E
f
)/RT
         (KT in ev) 
• No. of holes  p = N
v
 e
-(E
f
-E
v
)/RT
• Mass action law  n
p
 = n
i
2
 = N
c
N
v
 e
-EG/KT
• Drift velocity  ???? d
 = µE  (for si ???? d
 = 10
7
 cm/sec)
• Hall voltage ???? H
 = 
B.I
w
e
 . Hall coefficient  R
H
 = 1/? .            ? ? charge density = qN
0
 = ne … 
• Conductivity  s = ?µ ;  µ = sR
H
 .
• Max value of electric field @ junction E
0
 =  -
q
?
si
N
d
. n
n0
 =  -
q
?
si
 N
A
. n
p0
 . 
• Charge storage @ junction  Q
+
 = - Q
-
 = qA x
n0
N
D
 =  qA x
p0
N
A
• Diffusion current densities  J
p
 = - q D
p
 
dp
dx
J
n
 = - q D
n
 
dn
dx
• Drift current Densities  = q(p µ
p
+ nµ
n
)E
• µ
p
 , µ
n
 decrease with increasing doping concentration .
•
D
n
µ
n
= 
D
p
µ
p
 = KT/q ˜ 25 mv @ 300 K 
• Carrier concentration in N-type silicon n
n0
 = N
D
 ;  p
n0
 = n
i
2
 / N
D
• Carrier concentration in P-type silicon p
p0
 = N
A
 ;  n
p0
 = n
i
2
 / N
A
• Junction built in voltage  V
0
 = V
T
 ln ?
???? ???? ???? ???? ???? ???? 2
? 
• Width of Depletion region  W
dep
 =  x
p
 + x
n
 = ?
2e
s
q
?
1
N
A
+
1
N
D
?(V
0
+ V
R
) 
* ?
2???? ???????? ???? = 12.93???? ???????????? ???????? ?  
•
x
n
x
p
 = 
N
A
N
D
 
• Charge stored in depletion region  q
J
 = 
q.N
A
 N
D
N
A
+N
D
 . A . W
dep
  
• Depletion capacitance  C
j
 = 
e
s
A
W
dep
 ;   C
j0
 = 
e
s
A
W
dep
/ V
R
=0
C
j
 = C
j0
/? 1 +
V
R
V
0
?
m
  C
j
 = 2C
j0
  (for forward Bias) 
• Forward current  I = I
p
+ I
n
 ;       I
p
 = Aq n
i
2
D
p
L
p
N
D
 ? ???? ???? /???? ???? - 1? 
I
n
 = Aq n
i
2
 
D
n
L
n
N
A
 ? ???? ???? /???? ???? - 1?  
• Saturation Current  I
s
 = Aq n
i
2
  ?
D
p
L
p
N
D
+
D
n
L
n
N
A
? 
• Minority carrier life time  t
p
 = L
p
2
 / D
p
  ;    t
n
 = L
n
2
 / D
n
Analog Circuits (Formula Notes/Short Notes)
• Minority carrier charge storage  Q
p
 = t
p
I
p
 ,  Q
n
 = t
p
I
n
     Q = Q
p
 + Q
n
 = t
T
I              t
T
 = mean transist time 
• Diffusion capacitance  C
d
 =  ?
???? ???? ???????? ???? ? I = t.g  ? C
d
 ? I. 
t? carrier life time ,  g = conductance = I /  ???????? ????  
• I
02
 = 2
(T
2
-T
1
)/10
 I
01
• Junction Barrier Voltage  V
j
 = V
B
 = V
r
 (open condition)
           = V
r
 - V (forward Bias) 
           =  V
r
 + V (Reverse Bias) 
• Probability of filled states above ‘E’  f(E) = 
1
1+e
(E-E
f
)/KT
  
• Drift velocity of  e
-
        ???? d
 = 10
7
 cm/sec 
• Poisson equation  
d
2
V
dx
2
 = 
-?
v
?
  = 
-nq
?
 ? 
dv
dx
 = E = 
-nqx
?
  
Transistor :- 
• I
E
 = I
DE
 + I
nE
• I
C
 = I
Co
 – a I
E
  ? Active region
• I
C
 = – a I
E
 + I
Co
 (1- e
V
C
/V
T
 )
Common Emitter :- 
• I
C
 = (1+ ß) I
Co
 + ßI
B
    ß = 
a
1-a
• I
CEO
 = 
I
Co
1-a
  ? Collector current when base open 
• I
CBO
 ? Collector current when I
E
 = 0        I
CBO
 > I
Co
 .
• V
BE,sat
  or  V
BC,sat
 ?  - 2.5 mv /
0
 C ;    V
CE,sat
 ? 
V
BE,sat
10
 = - 0.25 mv /
0
C 
• Large signal Current gain  ß =  
I
C
- I
CBo
I
B
+ I
CBo
• D.C current gain  ß
dc
 = 
I
C
I
B
 = h
FE
  
• (ß
dc
 = h
FE
 ) ˜ ß   when  I
B
 > I
CBo
• Small signal current gain ß
'
 = 
?I
C
?I
R
?
V
CE
 =  h
fe
 =  
h
FE
1-(I
CBo
+ I
B
)
?h
FE
?I
C
  
• Over drive factor =
ß
active
ß
forced
?under saturation
 ? I
C sat
 = ß
forced
 I
B sat
   
Conversion formula :- 
   CC  ? CE 
• h
ic
 = h
ie
 ;     h
rc
 = 1 ;         h
fc
 = - (1+ h
fe
) ;      h
oc
 = h
oe
 
 CB  ? CE 
• h
ib
 = 
h
ie
1+h
fe
;  h
ib
 = 
h
ie
 h
oe
1+h
fe
- h
re
 ; h
fb
 = 
-h
fe
1+h
fe
;    h
ob
 = 
h
oe
1+h
fe
CE parameters in terms of CB can be obtained by interchanging B & E . 
• A
I
 =
-h
f
1+h
0
Z
L
 Z
i
 = h
i
 + h
r
 A
I
Z
L
          A
vs
 = 
A
v
.Z
i
Z
i
+R
s
Z
i
+R
s
 = 
A
I
.Z
L
 = 
A
I
s
.Z
L
R
s
A
V
 = 
A
I
  Z
L
Z
i
Y
0
 = h
o
 - 
h
f
 h
r
h
i
+ R
s
A
Is
 = 
A
v
.R
s
Z
i
+R
s
  = 
A
vs
.R
s
Z
L
  
Choice of Transistor Configuration :- 
• For intermediate stages CC can’t be used as  A
V
 < 1
• CE can be used as intermediate stage
• CC can be used as o/p stage as it has low o/p impedance
• CC/CB can be used as i/p stage because of i/p considerations.
Stability & Biasing :- ( Should be as min as possible) 
• For  S = 
?I
C
?I
Co
?
V
B0,ß
    S
'
 = 
?I
C
?V
BE
?
I
C0,ß
          S
''
 = 
?I
C
?ß
?
V
BE,I
Co
 ?I
C
 = S. ?I
Co
  + S
'
 ?V
BE
 + S
''
 ?ß  
• For fixed bias  S =
1+ß
1-ß
dI
B
dI
C
  = 1 + ß  
• Collector to Base bias  S = 
1+ß
1+ß
R
C
R
C
+R
B
           0 < s < 1+ ß  = 
1+ß
1+ß?
R
C
+ R
E
R
C
+ R
E
+ R
B
?
• Self bias  S =  
1+ß
1+ß
R
E
R
E
+R
th
  ˜ 1+ 
R
th
R
e
          ßR
E
  > 10 R
2
 
• R
1
 = 
V
cc
 R
th
V
th
;  R
2
 = 
V
cc
 R
th
V
cc
-V
th
• For thermal stability [ V
cc
 - 2I
c
 (R
C
 + R
E
)] [ 0.07 I
co
 . S]  <  1/?  ; V
CE
 < 
V
CC
2
Hybrid –pi(p)- Model :- 
  g
m
 = |I
C
 | / V
T
   
 r
b
'
e
  =  h
fe
 / g
m
         
r
b
'
b
 = h
ie
 - r
b
'
e
r
b
'
c
 = r
b
'
e
 / h
re
        
g
ce
 = h
oe
 - (1+ h
fe
 ) g
b
'
c
    
Specifications of An amplifier :- 
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FAQs on Analog Circuits Formulas for GATE ECE Exam - Analog Circuits - Electronics and Communication Engineering (ECE)

1. What are some important analog circuit formulas for the GATE ECE exam in Electronics and Communication Engineering (ECE)?
Ans. Some important analog circuit formulas for the GATE ECE exam in Electronics and Communication Engineering (ECE) include: - Ohm's Law: V = IR, where V is the voltage across a resistor, I is the current flowing through the resistor, and R is the resistance. - Kirchhoff's Current Law (KCL): The sum of currents entering a node in a circuit is equal to the sum of currents leaving that node. - Kirchhoff's Voltage Law (KVL): The sum of voltages around a closed loop in a circuit is zero. - Thevenin's Theorem: Any linear circuit with voltage and current sources and resistors can be replaced by an equivalent circuit consisting of a single voltage source and a single resistor. - Norton's Theorem: Any linear circuit with voltage and current sources and resistors can be replaced by an equivalent circuit consisting of a single current source and a single resistor.
2. How are these analog circuit formulas relevant to the GATE ECE exam?
Ans. These analog circuit formulas are fundamental principles that every Electronics and Communication Engineering (ECE) student should be familiar with. They form the basis for analyzing and solving problems in analog circuits, which are an important part of the GATE ECE exam syllabus. Understanding and applying these formulas is essential for solving circuit analysis questions and designing analog circuits.
3. What is the significance of Ohm's Law in analog circuits?
Ans. Ohm's Law is one of the most fundamental formulas in analog circuits. It relates the voltage across a resistor to the current flowing through it and the resistance value. This law is crucial for calculating the current or voltage in a circuit, determining the power dissipated by a resistor, and understanding the behavior of resistive elements in various circuit configurations. Ohm's Law is extensively used in analyzing and designing circuits, making it essential knowledge for the GATE ECE exam.
4. How can Kirchhoff's laws be applied in analog circuit analysis?
Ans. Kirchhoff's Current Law (KCL) and Kirchhoff's Voltage Law (KVL) are essential tools for analyzing complex analog circuits. KCL states that the algebraic sum of currents entering a node in a circuit is equal to the sum of currents leaving that node. KVL states that the algebraic sum of voltages around a closed loop in a circuit is zero. By applying these laws, one can set up and solve a system of equations representing the circuit, enabling the determination of unknown currents or voltages. Knowledge of Kirchhoff's laws is crucial for solving circuit analysis problems in the GATE ECE exam.
5. How do Thevenin's and Norton's theorems simplify circuit analysis in the GATE ECE exam?
Ans. Thevenin's Theorem and Norton's Theorem are powerful techniques used to simplify complex analog circuits. Thevenin's Theorem states that any linear circuit with voltage and current sources and resistors can be replaced by an equivalent circuit consisting of a single voltage source and a single resistor. Norton's Theorem states that any linear circuit with voltage and current sources and resistors can be replaced by an equivalent circuit consisting of a single current source and a single resistor. These theorems allow for the reduction of a circuit to a simpler form, making analysis easier and more efficient. Understanding and applying Thevenin's and Norton's theorems are valuable skills for solving circuit analysis problems in the GATE ECE exam.
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