Short Notes: I/O Interface(Interrupt and DMA Mode) | Short Notes for Computer Science Engineering - Computer Science Engineering (CSE) PDF Download

 Page 1


• The I/O system provides an efficient mode of communication between the 
central system and the outside environment.
• Programs and data must be entered into computer memory for processing 
end results obtained from computations must be displayed for the user. The 
most familiar means of entering information into a computer is through a type 
writer-like keyboard. On the other hand the central processing unit is an 
extremely fast device capable of performing operations at very high speed.
• To use a computer efficiently, a large amount of programs and data must be 
prepared in advance and transmitted into a storage medium such as magnetic 
tapes or disks. The information in the disk is then transferred into a high­
speed storage, such as disks.
• Input or output devices attached to the computer are called the peripheral 
devices. The most common peripherals are keyboards, display units and 
printers. Peripherals that provide auxiliary storage for the system are 
magnetic disks and tapes.
Input-Output Interface
• Input-Output interface provides a method for transferring information between 
internal storage and external I/O devices.
• Peripherals are connected to the central processing unit with a special 
communication links (I/O bus).
• The I/O bus from processor is attached to all peripheral interfaces.
Page 2


• The I/O system provides an efficient mode of communication between the 
central system and the outside environment.
• Programs and data must be entered into computer memory for processing 
end results obtained from computations must be displayed for the user. The 
most familiar means of entering information into a computer is through a type 
writer-like keyboard. On the other hand the central processing unit is an 
extremely fast device capable of performing operations at very high speed.
• To use a computer efficiently, a large amount of programs and data must be 
prepared in advance and transmitted into a storage medium such as magnetic 
tapes or disks. The information in the disk is then transferred into a high­
speed storage, such as disks.
• Input or output devices attached to the computer are called the peripheral 
devices. The most common peripherals are keyboards, display units and 
printers. Peripherals that provide auxiliary storage for the system are 
magnetic disks and tapes.
Input-Output Interface
• Input-Output interface provides a method for transferring information between 
internal storage and external I/O devices.
• Peripherals are connected to the central processing unit with a special 
communication links (I/O bus).
• The I/O bus from processor is attached to all peripheral interfaces.
1/0 Communication
¦ There is a need of I/O bus for communication between CPU and peripheral 
devices because o f many reasons
(a) Data formats o f internal memory of CPU and the peripheral devices (I/O 
devices) are different.
(b) Data transfer rates CPU and the I/O devices are different.
Asynchronous Data Transfer
• The two units such as CPU and I/O interface, are designed independently of 
each other. If the registers in the interface does not have a common clock 
(global clock) with the CPU registers, then the transfer between the two units 
is said to be asynchronous.
Classification ol asynchronous data transfer 
approach
• The asynchronous data transfer requires the control signals that are being 
transmitted between the communicating units to indicate the time at which 
data is being transmitted.
Strobe Control
• Strobe is a pulse signal supplied by one unit to another unit to indicate the 
time at which data is being transmitted.
Bloch diagram Bloch diagram
Data In v a lid dalasi_________ Data [? valid data-»-l_________
Strobe 1 ^-Valid dala-^l_________ Strobe In va lid d a t a    
Timing diagram Timing diagram
Source initiated strobe for data Destination initiated for data transfer 
transfer
• Strobe may be activated by either the source or the destination unit.
• The strobe pulse is controlled by the clock pulses in the CPU. The data bus 
carries the binary information from source unit to the destination unit. In 
source initiated strobe for data transfer, the strobe is a single line that 
informs the destination unit when a valid data word is available in the bus.
• But in destination initiated for data transfer it informs the source to provide 
the data. Then source unit places the data on the data bus.
Handshaking
• The disadvantage of the strobe method is that the source unit has no 
information whether the destination unit has actually received the data item, if 
the source unit initiates the transfer. But if the destination unit initiates the
Page 3


• The I/O system provides an efficient mode of communication between the 
central system and the outside environment.
• Programs and data must be entered into computer memory for processing 
end results obtained from computations must be displayed for the user. The 
most familiar means of entering information into a computer is through a type 
writer-like keyboard. On the other hand the central processing unit is an 
extremely fast device capable of performing operations at very high speed.
• To use a computer efficiently, a large amount of programs and data must be 
prepared in advance and transmitted into a storage medium such as magnetic 
tapes or disks. The information in the disk is then transferred into a high­
speed storage, such as disks.
• Input or output devices attached to the computer are called the peripheral 
devices. The most common peripherals are keyboards, display units and 
printers. Peripherals that provide auxiliary storage for the system are 
magnetic disks and tapes.
Input-Output Interface
• Input-Output interface provides a method for transferring information between 
internal storage and external I/O devices.
• Peripherals are connected to the central processing unit with a special 
communication links (I/O bus).
• The I/O bus from processor is attached to all peripheral interfaces.
1/0 Communication
¦ There is a need of I/O bus for communication between CPU and peripheral 
devices because o f many reasons
(a) Data formats o f internal memory of CPU and the peripheral devices (I/O 
devices) are different.
(b) Data transfer rates CPU and the I/O devices are different.
Asynchronous Data Transfer
• The two units such as CPU and I/O interface, are designed independently of 
each other. If the registers in the interface does not have a common clock 
(global clock) with the CPU registers, then the transfer between the two units 
is said to be asynchronous.
Classification ol asynchronous data transfer 
approach
• The asynchronous data transfer requires the control signals that are being 
transmitted between the communicating units to indicate the time at which 
data is being transmitted.
Strobe Control
• Strobe is a pulse signal supplied by one unit to another unit to indicate the 
time at which data is being transmitted.
Bloch diagram Bloch diagram
Data In v a lid dalasi_________ Data [? valid data-»-l_________
Strobe 1 ^-Valid dala-^l_________ Strobe In va lid d a t a    
Timing diagram Timing diagram
Source initiated strobe for data Destination initiated for data transfer 
transfer
• Strobe may be activated by either the source or the destination unit.
• The strobe pulse is controlled by the clock pulses in the CPU. The data bus 
carries the binary information from source unit to the destination unit. In 
source initiated strobe for data transfer, the strobe is a single line that 
informs the destination unit when a valid data word is available in the bus.
• But in destination initiated for data transfer it informs the source to provide 
the data. Then source unit places the data on the data bus.
Handshaking
• The disadvantage of the strobe method is that the source unit has no 
information whether the destination unit has actually received the data item, if 
the source unit initiates the transfer. But if the destination unit initiates the
transfer it has no way of knowing whether the source unit has actually placed 
the data on the bus. The handshake method solves this problem.
• The basic approach of handshaking is as follows. In handshaking method, 
there are two control signals unlike strobe control method. One control signal 
is in the same direction as the data flow in the bus from the source to the 
destination. This signal is used to inform the destination unit whether there 
are valid data in the bus. The second control signal is in the other direction 
from the destination to the source. It is used to inform the source whether it 
can accept data.
Data bus
Source
unit
Data valid Destination
unit
Data accepted
Block diagranj of handshaking
Synchronous Data Transfer
In synchronous data transfer a global or shared clock is provided to both sender 
and receiver. The sender and receiver works simultaneously.
Modes of Transfer
The information from external device is stored in memory. Information transferred 
from the central computer into an external device via memory unit. Hence, this data 
transfer between the central computer and I/O devices is handled in various 
modes.
1. Programmed I/O
2. Interrupt- initiated I/O
3. Direct Memory Access (DMA)
Programmed I/O: In this mode, each data item is transferred by an instruction in 
the program. The CPU issues a command then waits for I/O operations to be 
complete.
As the CPU is faster than the I/O module, the problem with programmed I/O is that 
the CPU has to wait a long time for the I/O module of concern to be ready for either 
reception or transmission of data.
Programmed I/O basically works in these ways:
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
The CPU, while waiting, must repeatedly check the status of the I/O module, and 
this process is known as Polling. As a result, the level of the performance of the 
entire system is severely degraded.
Page 4


• The I/O system provides an efficient mode of communication between the 
central system and the outside environment.
• Programs and data must be entered into computer memory for processing 
end results obtained from computations must be displayed for the user. The 
most familiar means of entering information into a computer is through a type 
writer-like keyboard. On the other hand the central processing unit is an 
extremely fast device capable of performing operations at very high speed.
• To use a computer efficiently, a large amount of programs and data must be 
prepared in advance and transmitted into a storage medium such as magnetic 
tapes or disks. The information in the disk is then transferred into a high­
speed storage, such as disks.
• Input or output devices attached to the computer are called the peripheral 
devices. The most common peripherals are keyboards, display units and 
printers. Peripherals that provide auxiliary storage for the system are 
magnetic disks and tapes.
Input-Output Interface
• Input-Output interface provides a method for transferring information between 
internal storage and external I/O devices.
• Peripherals are connected to the central processing unit with a special 
communication links (I/O bus).
• The I/O bus from processor is attached to all peripheral interfaces.
1/0 Communication
¦ There is a need of I/O bus for communication between CPU and peripheral 
devices because o f many reasons
(a) Data formats o f internal memory of CPU and the peripheral devices (I/O 
devices) are different.
(b) Data transfer rates CPU and the I/O devices are different.
Asynchronous Data Transfer
• The two units such as CPU and I/O interface, are designed independently of 
each other. If the registers in the interface does not have a common clock 
(global clock) with the CPU registers, then the transfer between the two units 
is said to be asynchronous.
Classification ol asynchronous data transfer 
approach
• The asynchronous data transfer requires the control signals that are being 
transmitted between the communicating units to indicate the time at which 
data is being transmitted.
Strobe Control
• Strobe is a pulse signal supplied by one unit to another unit to indicate the 
time at which data is being transmitted.
Bloch diagram Bloch diagram
Data In v a lid dalasi_________ Data [? valid data-»-l_________
Strobe 1 ^-Valid dala-^l_________ Strobe In va lid d a t a    
Timing diagram Timing diagram
Source initiated strobe for data Destination initiated for data transfer 
transfer
• Strobe may be activated by either the source or the destination unit.
• The strobe pulse is controlled by the clock pulses in the CPU. The data bus 
carries the binary information from source unit to the destination unit. In 
source initiated strobe for data transfer, the strobe is a single line that 
informs the destination unit when a valid data word is available in the bus.
• But in destination initiated for data transfer it informs the source to provide 
the data. Then source unit places the data on the data bus.
Handshaking
• The disadvantage of the strobe method is that the source unit has no 
information whether the destination unit has actually received the data item, if 
the source unit initiates the transfer. But if the destination unit initiates the
transfer it has no way of knowing whether the source unit has actually placed 
the data on the bus. The handshake method solves this problem.
• The basic approach of handshaking is as follows. In handshaking method, 
there are two control signals unlike strobe control method. One control signal 
is in the same direction as the data flow in the bus from the source to the 
destination. This signal is used to inform the destination unit whether there 
are valid data in the bus. The second control signal is in the other direction 
from the destination to the source. It is used to inform the source whether it 
can accept data.
Data bus
Source
unit
Data valid Destination
unit
Data accepted
Block diagranj of handshaking
Synchronous Data Transfer
In synchronous data transfer a global or shared clock is provided to both sender 
and receiver. The sender and receiver works simultaneously.
Modes of Transfer
The information from external device is stored in memory. Information transferred 
from the central computer into an external device via memory unit. Hence, this data 
transfer between the central computer and I/O devices is handled in various 
modes.
1. Programmed I/O
2. Interrupt- initiated I/O
3. Direct Memory Access (DMA)
Programmed I/O: In this mode, each data item is transferred by an instruction in 
the program. The CPU issues a command then waits for I/O operations to be 
complete.
As the CPU is faster than the I/O module, the problem with programmed I/O is that 
the CPU has to wait a long time for the I/O module of concern to be ready for either 
reception or transmission of data.
Programmed I/O basically works in these ways:
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
The CPU, while waiting, must repeatedly check the status of the I/O module, and 
this process is known as Polling. As a result, the level of the performance of the 
entire system is severely degraded.
Interrupt-initiated I/O: This mode removes the drawback of the programmed I/O 
mode. The CPU issues commands to the I/O module then proceeds with its normal 
work until interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to 
be retrieved by the system processor. The actual actions to perform depend on 
whether the device uses I/O ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new 
data or to acknowledge a successful data transfer. Memory-mapped and DMA- 
capable devices usually generate interrupts to tell the system they are done with 
the buffer.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still 
inefficient in data transfer of large amount because the CPU has to transfer the 
data word by word between I/O module and memory.
Below are the basic operations of Interrupt:
• CPU issues read command
• I/O module gets data from peripheral whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
Direct Memory Access (DMA)
Direct Memory Access (DMA) means CPU grants I/O module authority to read from 
or write to memory without involvement. DMA module controls exchange of data 
between main memory and the I/O device. Because of DMA device can transfer 
data directly to and from memory, rather than using the CPU as an intermediary, 
and can thus relieve congestion on the bus. CPU is only involved at the beginning 
and end of the transfer and interrupted only after entire block has been transferred. 
DMA is efficient for moving large amounts of data between I/O devices and main 
memory. It is considered efficient because it removes the CPU from being 
responsible for transferring data. DMA instructs the device controller to move data 
between the devices and main memory.
The CPU initiates the transfer by supplying the interface with the starting address 
and the number of words needed to be transferred and then proceeds to execute 
other tasks. When the transfer is made, the DMA requests memory cycles through 
the memory bus. When the request is granted by the memory controller, the DMA 
transfers the data directly into memory.
The Bus Request (BR) input is used by the DMA controller to request the CPU to get 
the control of buses. When this input is active, the CPU terminates the execution of 
the current instruction and places the address bus and the data bus. The CPU 
activates the Bus Grant (BG) output to inform the external DMA that the buses are 
available. The DMA now takes the control of the buses to conduct the memory 
transfer. When DMA terminates the transfer, it disables the bus request line. The 
CPU disables the bus grant, takes the control of the buses.
Bus Request— 
Bus Grant ¦ * -
B R
BG
CPU
ABUS
DBU S
RD
WR
? Address bus 
*• Data bus
* Read 
+ ¦ Write
CPU bus signals for DMA transfer
Page 5


• The I/O system provides an efficient mode of communication between the 
central system and the outside environment.
• Programs and data must be entered into computer memory for processing 
end results obtained from computations must be displayed for the user. The 
most familiar means of entering information into a computer is through a type 
writer-like keyboard. On the other hand the central processing unit is an 
extremely fast device capable of performing operations at very high speed.
• To use a computer efficiently, a large amount of programs and data must be 
prepared in advance and transmitted into a storage medium such as magnetic 
tapes or disks. The information in the disk is then transferred into a high­
speed storage, such as disks.
• Input or output devices attached to the computer are called the peripheral 
devices. The most common peripherals are keyboards, display units and 
printers. Peripherals that provide auxiliary storage for the system are 
magnetic disks and tapes.
Input-Output Interface
• Input-Output interface provides a method for transferring information between 
internal storage and external I/O devices.
• Peripherals are connected to the central processing unit with a special 
communication links (I/O bus).
• The I/O bus from processor is attached to all peripheral interfaces.
1/0 Communication
¦ There is a need of I/O bus for communication between CPU and peripheral 
devices because o f many reasons
(a) Data formats o f internal memory of CPU and the peripheral devices (I/O 
devices) are different.
(b) Data transfer rates CPU and the I/O devices are different.
Asynchronous Data Transfer
• The two units such as CPU and I/O interface, are designed independently of 
each other. If the registers in the interface does not have a common clock 
(global clock) with the CPU registers, then the transfer between the two units 
is said to be asynchronous.
Classification ol asynchronous data transfer 
approach
• The asynchronous data transfer requires the control signals that are being 
transmitted between the communicating units to indicate the time at which 
data is being transmitted.
Strobe Control
• Strobe is a pulse signal supplied by one unit to another unit to indicate the 
time at which data is being transmitted.
Bloch diagram Bloch diagram
Data In v a lid dalasi_________ Data [? valid data-»-l_________
Strobe 1 ^-Valid dala-^l_________ Strobe In va lid d a t a    
Timing diagram Timing diagram
Source initiated strobe for data Destination initiated for data transfer 
transfer
• Strobe may be activated by either the source or the destination unit.
• The strobe pulse is controlled by the clock pulses in the CPU. The data bus 
carries the binary information from source unit to the destination unit. In 
source initiated strobe for data transfer, the strobe is a single line that 
informs the destination unit when a valid data word is available in the bus.
• But in destination initiated for data transfer it informs the source to provide 
the data. Then source unit places the data on the data bus.
Handshaking
• The disadvantage of the strobe method is that the source unit has no 
information whether the destination unit has actually received the data item, if 
the source unit initiates the transfer. But if the destination unit initiates the
transfer it has no way of knowing whether the source unit has actually placed 
the data on the bus. The handshake method solves this problem.
• The basic approach of handshaking is as follows. In handshaking method, 
there are two control signals unlike strobe control method. One control signal 
is in the same direction as the data flow in the bus from the source to the 
destination. This signal is used to inform the destination unit whether there 
are valid data in the bus. The second control signal is in the other direction 
from the destination to the source. It is used to inform the source whether it 
can accept data.
Data bus
Source
unit
Data valid Destination
unit
Data accepted
Block diagranj of handshaking
Synchronous Data Transfer
In synchronous data transfer a global or shared clock is provided to both sender 
and receiver. The sender and receiver works simultaneously.
Modes of Transfer
The information from external device is stored in memory. Information transferred 
from the central computer into an external device via memory unit. Hence, this data 
transfer between the central computer and I/O devices is handled in various 
modes.
1. Programmed I/O
2. Interrupt- initiated I/O
3. Direct Memory Access (DMA)
Programmed I/O: In this mode, each data item is transferred by an instruction in 
the program. The CPU issues a command then waits for I/O operations to be 
complete.
As the CPU is faster than the I/O module, the problem with programmed I/O is that 
the CPU has to wait a long time for the I/O module of concern to be ready for either 
reception or transmission of data.
Programmed I/O basically works in these ways:
• CPU requests I/O operation
• I/O module performs operation
• I/O module sets status bits
• CPU checks status bits periodically
• I/O module does not inform CPU directly
• I/O module does not interrupt CPU
• CPU may wait or come back later
The CPU, while waiting, must repeatedly check the status of the I/O module, and 
this process is known as Polling. As a result, the level of the performance of the 
entire system is severely degraded.
Interrupt-initiated I/O: This mode removes the drawback of the programmed I/O 
mode. The CPU issues commands to the I/O module then proceeds with its normal 
work until interrupted by I/O device on completion of its work.
For input, the device interrupts the CPU when new data has arrived and is ready to 
be retrieved by the system processor. The actual actions to perform depend on 
whether the device uses I/O ports, memory mapping.
For output, the device delivers an interrupt either when it is ready to accept new 
data or to acknowledge a successful data transfer. Memory-mapped and DMA- 
capable devices usually generate interrupts to tell the system they are done with 
the buffer.
Although Interrupt relieves the CPU of having to wait for the devices, but it is still 
inefficient in data transfer of large amount because the CPU has to transfer the 
data word by word between I/O module and memory.
Below are the basic operations of Interrupt:
• CPU issues read command
• I/O module gets data from peripheral whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data
Direct Memory Access (DMA)
Direct Memory Access (DMA) means CPU grants I/O module authority to read from 
or write to memory without involvement. DMA module controls exchange of data 
between main memory and the I/O device. Because of DMA device can transfer 
data directly to and from memory, rather than using the CPU as an intermediary, 
and can thus relieve congestion on the bus. CPU is only involved at the beginning 
and end of the transfer and interrupted only after entire block has been transferred. 
DMA is efficient for moving large amounts of data between I/O devices and main 
memory. It is considered efficient because it removes the CPU from being 
responsible for transferring data. DMA instructs the device controller to move data 
between the devices and main memory.
The CPU initiates the transfer by supplying the interface with the starting address 
and the number of words needed to be transferred and then proceeds to execute 
other tasks. When the transfer is made, the DMA requests memory cycles through 
the memory bus. When the request is granted by the memory controller, the DMA 
transfers the data directly into memory.
The Bus Request (BR) input is used by the DMA controller to request the CPU to get 
the control of buses. When this input is active, the CPU terminates the execution of 
the current instruction and places the address bus and the data bus. The CPU 
activates the Bus Grant (BG) output to inform the external DMA that the buses are 
available. The DMA now takes the control of the buses to conduct the memory 
transfer. When DMA terminates the transfer, it disables the bus request line. The 
CPU disables the bus grant, takes the control of the buses.
Bus Request— 
Bus Grant ¦ * -
B R
BG
CPU
ABUS
DBU S
RD
WR
? Address bus 
*• Data bus
* Read 
+ ¦ Write
CPU bus signals for DMA transfer
Hardware design is complicated because the DMA controller must be integrated 
into the system, and the system must allow the DMA controller to be a bus master. 
Cycle stealing may also be necessary to allow the CPU and DMA controller to share 
use of the memory bus.
During a block input byte transfer, the following sequence occurs as the data byte 
is sent from the interface to the memory:
• The interface sends the DMA controller a request for DMA service.
• A Bus request is made to the HOLD pin (active High) on processor and the 
controller gains control of the bus.
• A Bus grant is returned to the DMA controller from the Hold Acknowledge 
(HLDA) pin (active High) on the processor.
• The DMA controller places contents of the address register onto the address 
bus.
• The controller sends the interface a DMA acknowledgment, which tells the 
interface to put data on the data bus. (For an output it signals the interface to 
latch the next data placed on the bus.)
• The data byte is transferred to the memory location indicated by the address 
bus.
• The interface latches the data.
• The Bus request is dropped, the HOLD pin goes Low, and the controller 
relinquishes the bus.
• The Bus grant from the processor is dropped and the HLDA pin goes Low.
• The address register is incremented by 1.
• The byte count is decremented by 1.
• If the byte count is non-zero, return to step 1, otherwise stop.
Types of Data transfers: The DMA Controller has several options available for the 
transfer of data. They are:
1. Cycle Steal: A read or write signal is generated by the DMAC, and the I/O 
device either generates or latches the data. The DMAC effectively steals 
cycles from the processor in order to transfer the byte, so single byte transfer 
is also known as cycle stealing.
2. Burst Transfer: To achieve block transfers, some DMAC's incorporate an 
automatic sequencing of the value presented on the address bus. A register is 
used as a byte count, being decremented for each byte transfer, and upon the 
byte count reaching zero, the DMAC will release the bus. When the DMAC 
operates in burst mode, the CPU is halted for the duration of the data transfer.
3. Hidden DMA: It is possible to perform hidden DMA, which is transparent to the 
normal operation of the CPU. In other words, the bus is grabbed by the DMAC 
when the processor is not using it. The DMAC monitors the execution of the 
processor, and when it recognizes the processor executing an instruction 
which has sufficient empty clock cycles to perform a byte transfer, it waits till 
the processor is decoding the op code, then grabs the bus during this time. 
The processor is not slowed down, but continues processing normally. 
Naturally, the data transfer by the DMAC must be completed before the 
processor starts.
Hard Disk Structure
Hard Disk is an electro-magnetic direct access storage component.