Formula Sheets Basics of Computer Design - Computer Architecture & Organisation (CAO)

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Basics of Computer Arc hitecture F orm ula Sheet
Computer Organization Basics
• Definition : Structure and b eha vior of computer system, including functional units (CPU, memory ,
I/O).
• V on Neumann Arc hitecture : Stored program concept, program and d ata in same memory .
• F unctional Units : CPU (ALU, CU), Main Memory , Input/Output, In terconnected via bus es.
• Instruction Cycle : F etc h, Deco de, Execute, Store.
• Cycle Time : T
cycle
=
1
f
, where f is clo c k frequency (Hz).
Represen tation of Basic Information
• Bit : Smallest unit, 0 or 1.
• Byte : 8 bits , 2
8
= 256 v alues.
• W ord Size : w bits (e.g., 32 or 64), m ax v alue 2
w
-1 (unsigned).
• Num b er Represen tation :
– Unsigned In teger: 0 to 2
w
-1 .
– Signed (2’s Complemen t): -2
w-1
to 2
w-1
-1 .
– 2’s Complemen t: Neg(x) = 2
w
-x or ~x+1 .
• Floating P oin t (IEEE 754) : V alue = (-1)
s
·M ·2
E
, where s is sign bit, M is man tissa, E is
exp onen t.
• Memory Size : S
memory
= 2
a
·S
w ord
, where a is address bits, S
w ord
is w ord size (b ytes).
Main Me mory Organization
• Memory Capacit y : C = 2
a
·w , where a is address lines, w is w ord size (bits).
• A ddress Space : 2
a
unique addresses, a = log
2
C for b yte-addressable memory .
• A ccess Time : T
access
, t ypically 10-100 ns for RAM.
• Memory Bandwidth : B =
w·f
bus
T access
, where f
bus
is bus frequency .
• Stored Program Concept : Instructions and data stored in same memory , fetc h time T
fetc h
=
T
access
.
• Cac he Hit Ratio : h =
N
hit
N
hit
+N miss
, effectiv e access time T
eff
=h·T
cac he
+(1-h)·T
main
.
Computer Instructions
• Instruction F ormat : Op co de (op eration) + Op erands (data/ad dress).
• Instruction Length : L
instr
, fixed (e.g., 32 bits in RISC) or v ariable (CISC).
• Instruction T yp es : Arithmetic, Logical, Data T ransfer, Con trol (Branc h/Jump).
• Instruction Execution Time : T
exec
=T
fetc h
+T
deco de
+T
execute
+T
store
.
• Instructions P er Second : IPS =
f
CPI
, where CPI is cycles p er instruction.
• MIPS : MIPS =
f
CPI·10
6
, where f is clo c k frequency (Hz).
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Page 2


Basics of Computer Arc hitecture F orm ula Sheet
Computer Organization Basics
• Definition : Structure and b eha vior of computer system, including functional units (CPU, memory ,
I/O).
• V on Neumann Arc hitecture : Stored program concept, program and d ata in same memory .
• F unctional Units : CPU (ALU, CU), Main Memory , Input/Output, In terconnected via bus es.
• Instruction Cycle : F etc h, Deco de, Execute, Store.
• Cycle Time : T
cycle
=
1
f
, where f is clo c k frequency (Hz).
Represen tation of Basic Information
• Bit : Smallest unit, 0 or 1.
• Byte : 8 bits , 2
8
= 256 v alues.
• W ord Size : w bits (e.g., 32 or 64), m ax v alue 2
w
-1 (unsigned).
• Num b er Represen tation :
– Unsigned In teger: 0 to 2
w
-1 .
– Signed (2’s Complemen t): -2
w-1
to 2
w-1
-1 .
– 2’s Complemen t: Neg(x) = 2
w
-x or ~x+1 .
• Floating P oin t (IEEE 754) : V alue = (-1)
s
·M ·2
E
, where s is sign bit, M is man tissa, E is
exp onen t.
• Memory Size : S
memory
= 2
a
·S
w ord
, where a is address bits, S
w ord
is w ord size (b ytes).
Main Me mory Organization
• Memory Capacit y : C = 2
a
·w , where a is address lines, w is w ord size (bits).
• A ddress Space : 2
a
unique addresses, a = log
2
C for b yte-addressable memory .
• A ccess Time : T
access
, t ypically 10-100 ns for RAM.
• Memory Bandwidth : B =
w·f
bus
T access
, where f
bus
is bus frequency .
• Stored Program Concept : Instructions and data stored in same memory , fetc h time T
fetc h
=
T
access
.
• Cac he Hit Ratio : h =
N
hit
N
hit
+N miss
, effectiv e access time T
eff
=h·T
cac he
+(1-h)·T
main
.
Computer Instructions
• Instruction F ormat : Op co de (op eration) + Op erands (data/ad dress).
• Instruction Length : L
instr
, fixed (e.g., 32 bits in RISC) or v ariable (CISC).
• Instruction T yp es : Arithmetic, Logical, Data T ransfer, Con trol (Branc h/Jump).
• Instruction Execution Time : T
exec
=T
fetc h
+T
deco de
+T
execute
+T
store
.
• Instructions P er Second : IPS =
f
CPI
, where CPI is cycles p er instruction.
• MIPS : MIPS =
f
CPI·10
6
, where f is clo c k frequency (Hz).
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F unctional Units
• CPU : ALU (arithmetic/logic), CU (con trol unit), Registers.
• Register A ccess Time : T
reg
«T
main
, t ypically 1-2 ns.
• ALU Op eration Time : T
ALU
, dep ends on op eration (e.g., add: 1 cycle, m ultiply: 2-4 cycles).
• Con trol Unit : Generates con trol signals, T
con trol
˜T
deco de
.
• Program Coun ter (PC) : PC = PC+L
instr
(sequen tial), or PC = target (branc h).
Bus Structure
• T yp es : Data Bus, A ddress Bus, Con trol Bus.
• Data Bus Width : w
data
, t ypically 32 or 64 bits, affects bandwidth B =w
data
·f
bus
.
• A ddress Bus Width : w
addr
, max addressable memory 2
w
addr
b ytes.
• Bus Cycle Time : T
bus
=
1
f
bus
, where f
bus
is bus frequency .
• Bus T ransfer Time : T
transfer
=T
bus
·?
S
data
w
data
? .
• Bus Arbitration Ov erhead : T
arb
, t ypically 1-2 c ycles for shared bus.
P erformance Metrics
• Clo c k F requency : f =
1
T
cycle
, measured in GHz.
• Cycles P er Instruction (CPI) : CPI =
?
(CPIi·Ni)
?
Ni
, where CPI
i
is cycles for instruction t yp e i ,
N
i
is coun t.
• Execution Time : T
exec
=
N· CPI
f
, where N is total instructions.
• Throughput : IPS =
f
CPI
, or MIPS =
IPS
10
6
.
• Amdahl’s La w : Sp eedupS =
1
(1-P)+
P
k
, whereP is parallelizable fraction,k is sp eedup of parallel
part.
• Memory Latency : T
mem
=T
access
+T
transfer
, reduced b y c ac he.
Applications and Concepts
• Stored Program : Enables flexibilit y , T
program-load
=
S program
B
, where B is memory bandwidth.
• Memory Hierarc h y : Registers (O(1) ns), Cac he (O(10) ns), Main Memory (O(100) ns), Disk
(O(10
6
) ns).
• Pip elining : Throughput ˜
f
1
, latency T
pip eline
=k·T
cycle
, where k is pip eline stages.
• Instruction Set Arc hitecture (ISA) : RISC (fixed-length, O(1) deco de) vs. CISC (v ariable-
length, O(1)-O(10) deco de).
• System P erformance : P erf?f ·(1- miss-rate)·
1
CPI
.
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