Formula Sheets: Machine Instructions & Addressing Modes | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) PDF Download

 Page 1


Mac hine Instructions and A ddressing Mo des F orm ula Sheet
Mac hine Instructions Basics
• Definition : Lo w-lev el commands executed b y CPU, part of Instruction Set Arc hitecture (ISA).
• Instruction Comp onen ts : Op co de (op eration co de) + Op erands (data/address).
• Instruction Length : L
instr
, fixed (RISC, e.g., 32 bits) or v ariable (CISC, e.g., 1-15 b ytes).
• Instruction T yp es : Arithmetic (ADD, SUB), Logical (AND, OR), Data T ransfer (MO V, LO AD),
Con trol (JMP , CALL).
• Instruction Execution Time : T
exec
=T
fetc h
+T
deco de
+T
op e rand
+T
execute
+T
store
.
• Cycles P er Instruction (CPI) : CPI =
?
(CPI
i
·f
i
) , where CPI
i
is cycles for instruction t yp e
i , f
i
is frequency .
Instruction F ormats
• Comp onen ts : Op co de (k bits), A ddress fields ( a
i
bits), Mo de fields ( m
i
bits).
• Num b er of Instructions : N
op co de
= 2
k
, where k is op co de bits.
• A ddress Space : A = 2
ai
p er address field i .
• Instruction F ormat T yp es :
– Zero-A ddress: Stac k-based, op erands on stac k, L
instr
=k .
– One-A ddress: A ccum ulator-based, L
instr
=k +a
1
.
– T w o-A ddress: L
instr
=k +a
1
+a
2
.
– Three-A ddress: L
instr
=k +a
1
+a
2
+a
3
.
• Simplified Instructional Computer (SIC) : Fixed 24-bit format, 8-bit op co de, 1-bit addressing
mo de, 15-bit address.
• Instruction Size : S
instr
=k +
?
a
i
+
?
m
i
, in bits.
A ddressing Mo des
• Effectiv e A ddress (EA) : A ctual memory address used, EA =f( mo de, address field ) .
• Common A ddressing Mo des :
– Immediate: EA = N/A, op erand = v alue in instruction, T
op eran d
= 0 .
– Direct: EA = address field, T
op erand
=T
mem
.
– Indirect: EA =M[ address field ] , T
op erand
= 2·T
mem
.
– Register: EA = N/A, op erand in register, T
op erand
=T
reg
.
– Register Indirect: EA =R[ register] , T
op erand
=T
reg
+T
mem
.
– Indexed: EA = address field +R[ index] , T
op erand
=T
reg
+T
mem
.
– Base-Register: EA = base address+ offset, T
op erand
=T
reg
.
– PC-Relativ e: EA = PC+ offset, T
op erand
=T
reg
, used f or branc hes.
– Stac k-Based: EA = stac k p oin ter (SP), T
op erand
=T
mem
.
• Mo de Field Size : m =?log
2
N
mo des
? bits, where N
mo des
is n um b er of mo des.
• A ddressing Time : T
op erand
? memory accesses, e.g., indirect > direct > immediate.
1
Page 2


Mac hine Instructions and A ddressing Mo des F orm ula Sheet
Mac hine Instructions Basics
• Definition : Lo w-lev el commands executed b y CPU, part of Instruction Set Arc hitecture (ISA).
• Instruction Comp onen ts : Op co de (op eration co de) + Op erands (data/address).
• Instruction Length : L
instr
, fixed (RISC, e.g., 32 bits) or v ariable (CISC, e.g., 1-15 b ytes).
• Instruction T yp es : Arithmetic (ADD, SUB), Logical (AND, OR), Data T ransfer (MO V, LO AD),
Con trol (JMP , CALL).
• Instruction Execution Time : T
exec
=T
fetc h
+T
deco de
+T
op e rand
+T
execute
+T
store
.
• Cycles P er Instruction (CPI) : CPI =
?
(CPI
i
·f
i
) , where CPI
i
is cycles for instruction t yp e
i , f
i
is frequency .
Instruction F ormats
• Comp onen ts : Op co de (k bits), A ddress fields ( a
i
bits), Mo de fields ( m
i
bits).
• Num b er of Instructions : N
op co de
= 2
k
, where k is op co de bits.
• A ddress Space : A = 2
ai
p er address field i .
• Instruction F ormat T yp es :
– Zero-A ddress: Stac k-based, op erands on stac k, L
instr
=k .
– One-A ddress: A ccum ulator-based, L
instr
=k +a
1
.
– T w o-A ddress: L
instr
=k +a
1
+a
2
.
– Three-A ddress: L
instr
=k +a
1
+a
2
+a
3
.
• Simplified Instructional Computer (SIC) : Fixed 24-bit format, 8-bit op co de, 1-bit addressing
mo de, 15-bit address.
• Instruction Size : S
instr
=k +
?
a
i
+
?
m
i
, in bits.
A ddressing Mo des
• Effectiv e A ddress (EA) : A ctual memory address used, EA =f( mo de, address field ) .
• Common A ddressing Mo des :
– Immediate: EA = N/A, op erand = v alue in instruction, T
op eran d
= 0 .
– Direct: EA = address field, T
op erand
=T
mem
.
– Indirect: EA =M[ address field ] , T
op erand
= 2·T
mem
.
– Register: EA = N/A, op erand in register, T
op erand
=T
reg
.
– Register Indirect: EA =R[ register] , T
op erand
=T
reg
+T
mem
.
– Indexed: EA = address field +R[ index] , T
op erand
=T
reg
+T
mem
.
– Base-Register: EA = base address+ offset, T
op erand
=T
reg
.
– PC-Relativ e: EA = PC+ offset, T
op erand
=T
reg
, used f or branc hes.
– Stac k-Based: EA = stac k p oin ter (SP), T
op erand
=T
mem
.
• Mo de Field Size : m =?log
2
N
mo des
? bits, where N
mo des
is n um b er of mo des.
• A ddressing Time : T
op erand
? memory accesses, e.g., indirect > direct > immediate.
1
RISC vs. CISC
• RISC (Reduced Instruction Set Computer) :
– Fixed-length instructions, L
instr
= 32 bits (t ypical).
– Simple instructions, CPI˜ 1 .
– Load/Store arc hitecture, only memory ops are LO AD/STORE.
– More registers, N
regs
= 32 or 64, reduces T
mem
.
– Pip elining e?iciency: Throughput ˜f , where f is clo c k frequency .
• CISC (Complex Instruction Set Computer) :
– V ariable-length instructions, L
instr
= 1-15 b ytes.
– Complex instructions, CPI = 2-10 .
– Memory-to-memory op erations, increases T
op erand
.
– F ew er registers, N
regs
= 8-16 .
– Deco de o v erhead: T
deco de
?L
instr
.
• Instruction Coun t : N
RISC
>N
CISC
, but T
exec-RISC
<T
exec-CISC
due to lo w er CPI.
Instruction Execution
• Instruction Cycle Time : T
cycle
=T
fetc h
+T
deco de
+T
op erand
+T
execute
+T
store
.
• F etc h Time : T
fetc h
=T
mem
, t ypically 10-100 ns (main memory).
• Deco de Time : T
deco de
, RISC: O(1) , CISC: O(L
instr
) .
• Execute Time : T
execute
, e.g., ADD: 1 cycle, MUL: 2-4 cycles.
• Program Coun ter Up date : PC = PC+L
instr
(sequen tial), PC = target (branc h).
• Branc h P enalt y : T
branc h
=k·T
cycle
, where k is pip eline flush cycles (e.g., 2-3).
Stac k and Register-Based CPU Organization
• Stac k-Based :
– Op erands on stac k, T
op erand
= 2·T
mem
(push/p op).
– Zero-address instructions, S
instr
=k .
– Stac k P oin ter (SP): T rac ks top, SP = SP±S
elemen t
.
• Register-Based :
– Op erands in registers, T
op erand
=T
reg
˜ 1-2 ns.
– T w o/Three-address instructions, S
instr
=k +
?
a
i
.
– Register File Size: S
regs
=N
regs
·w , where w is w ord size (e.g., 32 b its).
• P erformance : Register-based faster due to T
reg
«T
mem
.
P erformance Metrics
• Execution Time : T
exec
=N · CPI·T
cycle
, where N is instruction coun t, T
cycle
=
1
f
.
• Throughput : I PS =
f
CPI
, MIPS =
IPS
10
6
.
• Amdahl’s La w : Sp eedupS =
1
(1-P)+
P
k
, whereP is parallelizable fraction,k is sp eedup of parallel
part.
• Instruction Bandwidth : B
instr
=
L instr·f
CPI
, in bits/s.
• A ddressing Ov erhead : T
addr
=T
mem
·N
access
, whereN
access
is memory accesses p er mo de (e.g.,
2 for indirect).
• Pip eline E?iciency : Throughput˜
f
1+ stalls
, stalls ? branc h mispredictions.
2
Page 3


Mac hine Instructions and A ddressing Mo des F orm ula Sheet
Mac hine Instructions Basics
• Definition : Lo w-lev el commands executed b y CPU, part of Instruction Set Arc hitecture (ISA).
• Instruction Comp onen ts : Op co de (op eration co de) + Op erands (data/address).
• Instruction Length : L
instr
, fixed (RISC, e.g., 32 bits) or v ariable (CISC, e.g., 1-15 b ytes).
• Instruction T yp es : Arithmetic (ADD, SUB), Logical (AND, OR), Data T ransfer (MO V, LO AD),
Con trol (JMP , CALL).
• Instruction Execution Time : T
exec
=T
fetc h
+T
deco de
+T
op e rand
+T
execute
+T
store
.
• Cycles P er Instruction (CPI) : CPI =
?
(CPI
i
·f
i
) , where CPI
i
is cycles for instruction t yp e
i , f
i
is frequency .
Instruction F ormats
• Comp onen ts : Op co de (k bits), A ddress fields ( a
i
bits), Mo de fields ( m
i
bits).
• Num b er of Instructions : N
op co de
= 2
k
, where k is op co de bits.
• A ddress Space : A = 2
ai
p er address field i .
• Instruction F ormat T yp es :
– Zero-A ddress: Stac k-based, op erands on stac k, L
instr
=k .
– One-A ddress: A ccum ulator-based, L
instr
=k +a
1
.
– T w o-A ddress: L
instr
=k +a
1
+a
2
.
– Three-A ddress: L
instr
=k +a
1
+a
2
+a
3
.
• Simplified Instructional Computer (SIC) : Fixed 24-bit format, 8-bit op co de, 1-bit addressing
mo de, 15-bit address.
• Instruction Size : S
instr
=k +
?
a
i
+
?
m
i
, in bits.
A ddressing Mo des
• Effectiv e A ddress (EA) : A ctual memory address used, EA =f( mo de, address field ) .
• Common A ddressing Mo des :
– Immediate: EA = N/A, op erand = v alue in instruction, T
op eran d
= 0 .
– Direct: EA = address field, T
op erand
=T
mem
.
– Indirect: EA =M[ address field ] , T
op erand
= 2·T
mem
.
– Register: EA = N/A, op erand in register, T
op erand
=T
reg
.
– Register Indirect: EA =R[ register] , T
op erand
=T
reg
+T
mem
.
– Indexed: EA = address field +R[ index] , T
op erand
=T
reg
+T
mem
.
– Base-Register: EA = base address+ offset, T
op erand
=T
reg
.
– PC-Relativ e: EA = PC+ offset, T
op erand
=T
reg
, used f or branc hes.
– Stac k-Based: EA = stac k p oin ter (SP), T
op erand
=T
mem
.
• Mo de Field Size : m =?log
2
N
mo des
? bits, where N
mo des
is n um b er of mo des.
• A ddressing Time : T
op erand
? memory accesses, e.g., indirect > direct > immediate.
1
RISC vs. CISC
• RISC (Reduced Instruction Set Computer) :
– Fixed-length instructions, L
instr
= 32 bits (t ypical).
– Simple instructions, CPI˜ 1 .
– Load/Store arc hitecture, only memory ops are LO AD/STORE.
– More registers, N
regs
= 32 or 64, reduces T
mem
.
– Pip elining e?iciency: Throughput ˜f , where f is clo c k frequency .
• CISC (Complex Instruction Set Computer) :
– V ariable-length instructions, L
instr
= 1-15 b ytes.
– Complex instructions, CPI = 2-10 .
– Memory-to-memory op erations, increases T
op erand
.
– F ew er registers, N
regs
= 8-16 .
– Deco de o v erhead: T
deco de
?L
instr
.
• Instruction Coun t : N
RISC
>N
CISC
, but T
exec-RISC
<T
exec-CISC
due to lo w er CPI.
Instruction Execution
• Instruction Cycle Time : T
cycle
=T
fetc h
+T
deco de
+T
op erand
+T
execute
+T
store
.
• F etc h Time : T
fetc h
=T
mem
, t ypically 10-100 ns (main memory).
• Deco de Time : T
deco de
, RISC: O(1) , CISC: O(L
instr
) .
• Execute Time : T
execute
, e.g., ADD: 1 cycle, MUL: 2-4 cycles.
• Program Coun ter Up date : PC = PC+L
instr
(sequen tial), PC = target (branc h).
• Branc h P enalt y : T
branc h
=k·T
cycle
, where k is pip eline flush cycles (e.g., 2-3).
Stac k and Register-Based CPU Organization
• Stac k-Based :
– Op erands on stac k, T
op erand
= 2·T
mem
(push/p op).
– Zero-address instructions, S
instr
=k .
– Stac k P oin ter (SP): T rac ks top, SP = SP±S
elemen t
.
• Register-Based :
– Op erands in registers, T
op erand
=T
reg
˜ 1-2 ns.
– T w o/Three-address instructions, S
instr
=k +
?
a
i
.
– Register File Size: S
regs
=N
regs
·w , where w is w ord size (e.g., 32 b its).
• P erformance : Register-based faster due to T
reg
«T
mem
.
P erformance Metrics
• Execution Time : T
exec
=N · CPI·T
cycle
, where N is instruction coun t, T
cycle
=
1
f
.
• Throughput : I PS =
f
CPI
, MIPS =
IPS
10
6
.
• Amdahl’s La w : Sp eedupS =
1
(1-P)+
P
k
, whereP is parallelizable fraction,k is sp eedup of parallel
part.
• Instruction Bandwidth : B
instr
=
L instr·f
CPI
, in bits/s.
• A ddressing Ov erhead : T
addr
=T
mem
·N
access
, whereN
access
is memory accesses p er mo de (e.g.,
2 for indirect).
• Pip eline E?iciency : Throughput˜
f
1+ stalls
, stalls ? branc h mispredictions.
2
Applications and Concepts
• V on Neumann Arc hitecture : Single memory for instructions/d ata, b ottlenec k T
mem
.
• 64-Bit Pro cessor : A ddress space 2
64
b ytes, w ord size 64 bits, S
regs
= 64·N
regs
.
• Microarc hitecture : Implemen ts ISA, aff ects T
cycle
and CPI.
• A ddressing Sequencing : Sequen tial (PC+L
instr
), Conditional (branc hes), Subroutine (CALL/RET).
• Instruction Set Design : RISC (simple, pip elined) vs. CISC (complex, compact co de).
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