PPT: Sequential Circuits | Digital Logic - Computer Science Engineering (CSE) PDF Download

 Page 1


Sequential 
Circuits
Page 2


Sequential 
Circuits
Latches & Their Types
SR Latch
Inputs: S (Set), R (Reset)
Outputs: Q, ¬Q
Truth Table: S=1, R=0 ³ Q=1; S=0, 
R=1 ³ Q=0; S=0, R=0 ³ Hold; S=1, 
R=1 ³ Invalid
D Latch
Input: D (Data)
Avoids invalid state of SR latch
Truth Table: D=1 ³ Q=1; D=0 ³ Q=0 
(when enabled)
Key Characteristics
Level-sensitive operation
Output changes based on input 
while enable signal is active
Implemented using NOR or 
NAND gates
Latches are the most basic memory elements in sequential circuits, storing a single bit of information. They respond 
to input changes while their enable signal is active, making them level-triggered devices that serve as building 
blocks for more complex memory elements.
Page 3


Sequential 
Circuits
Latches & Their Types
SR Latch
Inputs: S (Set), R (Reset)
Outputs: Q, ¬Q
Truth Table: S=1, R=0 ³ Q=1; S=0, 
R=1 ³ Q=0; S=0, R=0 ³ Hold; S=1, 
R=1 ³ Invalid
D Latch
Input: D (Data)
Avoids invalid state of SR latch
Truth Table: D=1 ³ Q=1; D=0 ³ Q=0 
(when enabled)
Key Characteristics
Level-sensitive operation
Output changes based on input 
while enable signal is active
Implemented using NOR or 
NAND gates
Latches are the most basic memory elements in sequential circuits, storing a single bit of information. They respond 
to input changes while their enable signal is active, making them level-triggered devices that serve as building 
blocks for more complex memory elements.
Flip-Flops & Their Types
SR Flip-Flop
Similar to SR latch but 
edge-triggered, 
avoiding rapid 
toggling during clock 
pulse
D Flip-Flop
Stores input D on 
clock edge; simplest 
and widely used for 
data storage
JK Flip-Flop
Inputs: J (Set), K 
(Reset); adds toggle 
functionality when 
J=K=1
T Flip-Flop
Input: T (Toggle); 
toggles output when 
T=1, holds when T=0
Flip-flops improve upon latches by changing state only at specific clock transitions (edges), making them more stable and 
predictable. This edge-triggered behavior is crucial for synchronous digital systems, allowing precise timing control and 
preventing unwanted state changes during clock cycles.
Page 4


Sequential 
Circuits
Latches & Their Types
SR Latch
Inputs: S (Set), R (Reset)
Outputs: Q, ¬Q
Truth Table: S=1, R=0 ³ Q=1; S=0, 
R=1 ³ Q=0; S=0, R=0 ³ Hold; S=1, 
R=1 ³ Invalid
D Latch
Input: D (Data)
Avoids invalid state of SR latch
Truth Table: D=1 ³ Q=1; D=0 ³ Q=0 
(when enabled)
Key Characteristics
Level-sensitive operation
Output changes based on input 
while enable signal is active
Implemented using NOR or 
NAND gates
Latches are the most basic memory elements in sequential circuits, storing a single bit of information. They respond 
to input changes while their enable signal is active, making them level-triggered devices that serve as building 
blocks for more complex memory elements.
Flip-Flops & Their Types
SR Flip-Flop
Similar to SR latch but 
edge-triggered, 
avoiding rapid 
toggling during clock 
pulse
D Flip-Flop
Stores input D on 
clock edge; simplest 
and widely used for 
data storage
JK Flip-Flop
Inputs: J (Set), K 
(Reset); adds toggle 
functionality when 
J=K=1
T Flip-Flop
Input: T (Toggle); 
toggles output when 
T=1, holds when T=0
Flip-flops improve upon latches by changing state only at specific clock transitions (edges), making them more stable and 
predictable. This edge-triggered behavior is crucial for synchronous digital systems, allowing precise timing control and 
preventing unwanted state changes during clock cycles.
Characteristic Equation & Excitation Table
Characteristic Equations
SR Flip-Flop: Q ¹ ª¡ = S + ¬R·Q ¹ (S·R = 0)
D Flip-Flop: Q ¹ ª¡ = D
JK Flip-Flop: Q ¹ ª¡ = J·¬Q ¹ + ¬K·Q ¹
T Flip-Flop: Q ¹ ª¡ = T ·Q ¹
Excitation Table (JK Flip-Flop)
Q ¹ Q ¹ ª¡ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Characteristic equations mathematically define how a flip-flop's next state (Q ¹ ª¡) depends on its current state (Q ¹) and 
inputs. These equations are essential for analyzing circuit behavior and designing sequential systems. Excitation tables 
complement these equations by showing what input values are needed to achieve desired state transitions.
Page 5


Sequential 
Circuits
Latches & Their Types
SR Latch
Inputs: S (Set), R (Reset)
Outputs: Q, ¬Q
Truth Table: S=1, R=0 ³ Q=1; S=0, 
R=1 ³ Q=0; S=0, R=0 ³ Hold; S=1, 
R=1 ³ Invalid
D Latch
Input: D (Data)
Avoids invalid state of SR latch
Truth Table: D=1 ³ Q=1; D=0 ³ Q=0 
(when enabled)
Key Characteristics
Level-sensitive operation
Output changes based on input 
while enable signal is active
Implemented using NOR or 
NAND gates
Latches are the most basic memory elements in sequential circuits, storing a single bit of information. They respond 
to input changes while their enable signal is active, making them level-triggered devices that serve as building 
blocks for more complex memory elements.
Flip-Flops & Their Types
SR Flip-Flop
Similar to SR latch but 
edge-triggered, 
avoiding rapid 
toggling during clock 
pulse
D Flip-Flop
Stores input D on 
clock edge; simplest 
and widely used for 
data storage
JK Flip-Flop
Inputs: J (Set), K 
(Reset); adds toggle 
functionality when 
J=K=1
T Flip-Flop
Input: T (Toggle); 
toggles output when 
T=1, holds when T=0
Flip-flops improve upon latches by changing state only at specific clock transitions (edges), making them more stable and 
predictable. This edge-triggered behavior is crucial for synchronous digital systems, allowing precise timing control and 
preventing unwanted state changes during clock cycles.
Characteristic Equation & Excitation Table
Characteristic Equations
SR Flip-Flop: Q ¹ ª¡ = S + ¬R·Q ¹ (S·R = 0)
D Flip-Flop: Q ¹ ª¡ = D
JK Flip-Flop: Q ¹ ª¡ = J·¬Q ¹ + ¬K·Q ¹
T Flip-Flop: Q ¹ ª¡ = T ·Q ¹
Excitation Table (JK Flip-Flop)
Q ¹ Q ¹ ª¡ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Characteristic equations mathematically define how a flip-flop's next state (Q ¹ ª¡) depends on its current state (Q ¹) and 
inputs. These equations are essential for analyzing circuit behavior and designing sequential systems. Excitation tables 
complement these equations by showing what input values are needed to achieve desired state transitions.
Edge-Triggered Latches
Positive Edge-Triggered
Changes state on rising edge of clock (0³1), ignoring input changes at other times
Negative Edge-Triggered
Changes state on falling edge of clock (1³0), providing alternative timing options
Advantages
Prevents race conditions during clock pulse and synchronizes state changes across circuits
Implementation
Combines latches with clock signal (e.g., master-slave configuration) for controlled timing
Edge-triggered flip-flops are essential for synchronous circuits, ensuring predictable timing by 
changing state only at specific clock transitions. For example, a D flip-flop with D=1 will set Q=1 
only when the clock rises, ignoring any changes to D during the rest of the clock cycle.