Formula Sheet: BJT - Biasing & Stabilization | Analog Circuits - Electronics and Communication Engineering (ECE) PDF Download

 Page 1


Formula Sheet for Transistor Biasing and
Stabilization (Analog and Digital Electronics) –
GATE
1. Basic Concepts
• Biasing: Settingastableoperatingcondition(Q-point)fortransistors(BJT,MOS-
FET).
• Stabilization: Ensuring Q-point remains stable against variations in temperature,
transistor parameters (ß, V
TH
), and supply voltage.
• Objectives: Maintain transistor in active region (ampli?ers) or switch between
cut-o?/saturation (digital).
2. BJT Biasing Con?gurations
2.1 Fixed Bias
• Base Current:
I
B
=
V
CC
-V
BE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
• Limitation: Poor stability due to ß variation.
2.2 Collector-to-Base Bias
• Base Current:
I
B
=
V
CC
-V
BE
-V
CE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
(R
C
+R
B
/(ß +1))
2.3 Voltage Divider Bias
• Base Voltage:
V
B
=V
CC
·
R
2
R
1
+R
2
1
Page 2


Formula Sheet for Transistor Biasing and
Stabilization (Analog and Digital Electronics) –
GATE
1. Basic Concepts
• Biasing: Settingastableoperatingcondition(Q-point)fortransistors(BJT,MOS-
FET).
• Stabilization: Ensuring Q-point remains stable against variations in temperature,
transistor parameters (ß, V
TH
), and supply voltage.
• Objectives: Maintain transistor in active region (ampli?ers) or switch between
cut-o?/saturation (digital).
2. BJT Biasing Con?gurations
2.1 Fixed Bias
• Base Current:
I
B
=
V
CC
-V
BE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
• Limitation: Poor stability due to ß variation.
2.2 Collector-to-Base Bias
• Base Current:
I
B
=
V
CC
-V
BE
-V
CE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
(R
C
+R
B
/(ß +1))
2.3 Voltage Divider Bias
• Base Voltage:
V
B
=V
CC
·
R
2
R
1
+R
2
1
• Emitter Voltage:
V
E
=V
B
-V
BE
• Emitter Current:
I
E
=
V
E
R
E
• Collector Current:
I
C
˜I
E
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
-I
E
R
E
• Condition for Stability: R
1
?R
2
«ßR
E
.
3. BJT Stability Factors
• Stability Factor (S) for I
CBO
(reverse saturation current):
S =
? I
C
? I
CBO
=1+ß·
R
B
R
B
+(ß +1)R
E
where R
B
=R
1
?R
2
(voltage divider) or R
B
(?xed/collector bias).
• Stability Factor for ß:
S
ß
=
? I
C
? ß
=I
B
·
1
1+ß·
R
E
R
B
+R
E
• Stability Factor for V
BE
:
S
V
BE
=
? I
C
? V
BE
=-
ß
R
B
+(ß +1)R
E
• Goal: Minimize S, S
ß
, S
V
BE
for stable Q-point.
4. MOSFET Biasing Con?gurations
4.1 Voltage Divider Bias
• Gate Voltage:
V
G
=V
DD
·
R
2
R
1
+R
2
• Source Voltage:
V
S
=I
D
R
S
• Gate-Source Voltage:
V
GS
=V
G
-V
S
2
Page 3


Formula Sheet for Transistor Biasing and
Stabilization (Analog and Digital Electronics) –
GATE
1. Basic Concepts
• Biasing: Settingastableoperatingcondition(Q-point)fortransistors(BJT,MOS-
FET).
• Stabilization: Ensuring Q-point remains stable against variations in temperature,
transistor parameters (ß, V
TH
), and supply voltage.
• Objectives: Maintain transistor in active region (ampli?ers) or switch between
cut-o?/saturation (digital).
2. BJT Biasing Con?gurations
2.1 Fixed Bias
• Base Current:
I
B
=
V
CC
-V
BE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
• Limitation: Poor stability due to ß variation.
2.2 Collector-to-Base Bias
• Base Current:
I
B
=
V
CC
-V
BE
-V
CE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
(R
C
+R
B
/(ß +1))
2.3 Voltage Divider Bias
• Base Voltage:
V
B
=V
CC
·
R
2
R
1
+R
2
1
• Emitter Voltage:
V
E
=V
B
-V
BE
• Emitter Current:
I
E
=
V
E
R
E
• Collector Current:
I
C
˜I
E
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
-I
E
R
E
• Condition for Stability: R
1
?R
2
«ßR
E
.
3. BJT Stability Factors
• Stability Factor (S) for I
CBO
(reverse saturation current):
S =
? I
C
? I
CBO
=1+ß·
R
B
R
B
+(ß +1)R
E
where R
B
=R
1
?R
2
(voltage divider) or R
B
(?xed/collector bias).
• Stability Factor for ß:
S
ß
=
? I
C
? ß
=I
B
·
1
1+ß·
R
E
R
B
+R
E
• Stability Factor for V
BE
:
S
V
BE
=
? I
C
? V
BE
=-
ß
R
B
+(ß +1)R
E
• Goal: Minimize S, S
ß
, S
V
BE
for stable Q-point.
4. MOSFET Biasing Con?gurations
4.1 Voltage Divider Bias
• Gate Voltage:
V
G
=V
DD
·
R
2
R
1
+R
2
• Source Voltage:
V
S
=I
D
R
S
• Gate-Source Voltage:
V
GS
=V
G
-V
S
2
• Drain Current (Saturation):
I
D
=
k
n
2
(V
GS
-V
TH
)
2
where k
n
=µ n
C
ox
W
L
.
• Drain-Source Voltage:
V
DS
=V
DD
-I
D
(R
D
+R
S
)
4.2 Drain Feedback Bias
• Gate Voltage:
V
G
=V
DD
-I
D
R
D
• Gate-Source Voltage: V
GS
=V
G
(if source grounded).
• Drain Current:
I
D
=
k
n
2
(V
DD
-I
D
R
D
-V
TH
)
2
5. MOSFET Stability
• Threshold Voltage Variation: V
TH
a?ected by temperature and body e?ect.
V
TH
=V
TH0
+?
(
v
|V
SB
+2? F
|-
v
|2? F
|
)
where ?: Body e?ect parameter, ? F
: Fermi potential.
• Stability: Achieved by setting V
GS
»V
TH
, using R
S
for feedback.
• Temperature E?ect: I
D
decreases with increasing temperature due to µ n
reduc-
tion.
6. Thermal Runaway (BJT)
• Cause: IncreaseinI
C
withtemperatureincreasespowerdissipation, furtherraising
temperature.
• Prevention: Use emitter resistor R
E
:
V
E
=I
E
R
E
stabilizes I
C
7. Load Line Analysis
• BJT (Common Emitter):
V
CE
=V
CC
-I
C
(R
C
+R
E
)
• MOSFET (Common Source):
V
DS
=V
DD
-I
D
(R
D
+R
S
)
• Q-point: Intersection of load line and transistor characteristic curve.
3
Page 4


Formula Sheet for Transistor Biasing and
Stabilization (Analog and Digital Electronics) –
GATE
1. Basic Concepts
• Biasing: Settingastableoperatingcondition(Q-point)fortransistors(BJT,MOS-
FET).
• Stabilization: Ensuring Q-point remains stable against variations in temperature,
transistor parameters (ß, V
TH
), and supply voltage.
• Objectives: Maintain transistor in active region (ampli?ers) or switch between
cut-o?/saturation (digital).
2. BJT Biasing Con?gurations
2.1 Fixed Bias
• Base Current:
I
B
=
V
CC
-V
BE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
• Limitation: Poor stability due to ß variation.
2.2 Collector-to-Base Bias
• Base Current:
I
B
=
V
CC
-V
BE
-V
CE
R
B
• Collector Current:
I
C
=ßI
B
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
(R
C
+R
B
/(ß +1))
2.3 Voltage Divider Bias
• Base Voltage:
V
B
=V
CC
·
R
2
R
1
+R
2
1
• Emitter Voltage:
V
E
=V
B
-V
BE
• Emitter Current:
I
E
=
V
E
R
E
• Collector Current:
I
C
˜I
E
• Collector-Emitter Voltage:
V
CE
=V
CC
-I
C
R
C
-I
E
R
E
• Condition for Stability: R
1
?R
2
«ßR
E
.
3. BJT Stability Factors
• Stability Factor (S) for I
CBO
(reverse saturation current):
S =
? I
C
? I
CBO
=1+ß·
R
B
R
B
+(ß +1)R
E
where R
B
=R
1
?R
2
(voltage divider) or R
B
(?xed/collector bias).
• Stability Factor for ß:
S
ß
=
? I
C
? ß
=I
B
·
1
1+ß·
R
E
R
B
+R
E
• Stability Factor for V
BE
:
S
V
BE
=
? I
C
? V
BE
=-
ß
R
B
+(ß +1)R
E
• Goal: Minimize S, S
ß
, S
V
BE
for stable Q-point.
4. MOSFET Biasing Con?gurations
4.1 Voltage Divider Bias
• Gate Voltage:
V
G
=V
DD
·
R
2
R
1
+R
2
• Source Voltage:
V
S
=I
D
R
S
• Gate-Source Voltage:
V
GS
=V
G
-V
S
2
• Drain Current (Saturation):
I
D
=
k
n
2
(V
GS
-V
TH
)
2
where k
n
=µ n
C
ox
W
L
.
• Drain-Source Voltage:
V
DS
=V
DD
-I
D
(R
D
+R
S
)
4.2 Drain Feedback Bias
• Gate Voltage:
V
G
=V
DD
-I
D
R
D
• Gate-Source Voltage: V
GS
=V
G
(if source grounded).
• Drain Current:
I
D
=
k
n
2
(V
DD
-I
D
R
D
-V
TH
)
2
5. MOSFET Stability
• Threshold Voltage Variation: V
TH
a?ected by temperature and body e?ect.
V
TH
=V
TH0
+?
(
v
|V
SB
+2? F
|-
v
|2? F
|
)
where ?: Body e?ect parameter, ? F
: Fermi potential.
• Stability: Achieved by setting V
GS
»V
TH
, using R
S
for feedback.
• Temperature E?ect: I
D
decreases with increasing temperature due to µ n
reduc-
tion.
6. Thermal Runaway (BJT)
• Cause: IncreaseinI
C
withtemperatureincreasespowerdissipation, furtherraising
temperature.
• Prevention: Use emitter resistor R
E
:
V
E
=I
E
R
E
stabilizes I
C
7. Load Line Analysis
• BJT (Common Emitter):
V
CE
=V
CC
-I
C
(R
C
+R
E
)
• MOSFET (Common Source):
V
DS
=V
DD
-I
D
(R
D
+R
S
)
• Q-point: Intersection of load line and transistor characteristic curve.
3
8. Compensation Techniques
• Diode Compensation (BJT): Diode in series with R
B
to compensate V
BE
vari-
ation.
V
diode
˜V
BE
• Thermistor Compensation: Thermistor in voltage divider to adjust V
B
.
• Current Mirror (MOSFET): Matches I
D
across transistors for stability.
9. Key Parameters
• BJT: ß, V
BE
˜ 0.7V, I
CBO
.
• MOSFET: V
TH
, k
n
, ?.
• Thermal Voltage: V
T
=
kT
q
˜ 25mV at 300 K.
10. Design Considerations
• BJT: Use R
E
for stability, ensure V
CE
> 0.2V (active region).
• MOSFET: Set V
GS
>V
TH
, optimize W/L for desired I
D
.
• Applications: Ampli?ers, switches, voltage regulators.
• Stability Trade-o?: Higher stability reduces gain; balance R
E
, R
S
.
4