Short Notes: MOSFET Biasing & Amplifiers- 2 | Analog Circuits - Electronics and Communication Engineering (ECE) PDF Download

 Page 1


MOSFET Biasing & Amplifiers
Metal-Oxide-Semiconductor Field-Effect T ransistor (MOSFET) biasing establishes a sta-
ble DC op erating condition (Q-p oin t) for amplification. Prop er biasing ensures the MOS-
FET op erates in the desired region, and amplifiers are designed for signal amplification
with minimal distortion.
1. MOSFET Op erating Regions
MOSFET s op erate in three regions:
• Cutoff : V
GS
<V
TH
, I
D
= 0 (transistor off ).
• T rio de (Linear): V
GS
>V
TH
, V
DS
<V
GS
-V
TH
, I
D
?V
DS
.
• Saturation: V
GS
> V
TH
, V
DS
= V
GS
-V
TH
, I
D
=
1
2
k
n
(V
GS
-V
TH
)
2
(1+?V
DS
) ,
where k
n
=µ
n
C
ox
W
L
, ? is the c hannel-length mo dulation parameter.
2. Biasing T ec hniques
Biasing sets the Q-p oin t in the saturation region for a mplification. Common metho ds for
n-c hannel enhancemen t MOSFET s include:
1. Fixed Bias:
• Gate v oltage V
G
is set b y a v oltage divider or fixed source.
• Drain curren t: I
D
=
1
2
k
n
(V
GS
-V
TH
)
2
.
• Drain-source v oltage: V
DS
=V
DD
-I
D
R
D
, where R
D
is the drain resistor.
• Dra wbac k: Sensitiv e to V
TH
and k
n
v ariations.
2. Self-Bias:
• A resistor R
S
is added b et w een source and ground.
• Gate-source v oltage: V
GS
=V
G
-I
D
R
S
.
• Drain curren t: Solv e I
D
=
1
2
k
n
(V
G
-I
D
R
S
-V
TH
)
2
.
• A dv an tage: Stabilizes I
D
against parameter v ariations.
3. V oltage Divider Bias:
• Resistors R
1
and R
2
form a v oltage divider for gate v oltage: V
G
=V
DD
R
2
R
1
+R
2
.
• Source v oltage: V
S
=I
D
R
S
.
• Gate-source v o ltage: V
GS
=V
G
-V
S
.
• Drain-source v oltage: V
DS
=V
DD
-I
D
(R
D
+R
S
) .
• A dv an tage: High stabilit y against V
TH
and temp erature v ariations.
3. MOSFET Amplifiers
MOSFET s are used in three amplifier configurations:
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Page 2


MOSFET Biasing & Amplifiers
Metal-Oxide-Semiconductor Field-Effect T ransistor (MOSFET) biasing establishes a sta-
ble DC op erating condition (Q-p oin t) for amplification. Prop er biasing ensures the MOS-
FET op erates in the desired region, and amplifiers are designed for signal amplification
with minimal distortion.
1. MOSFET Op erating Regions
MOSFET s op erate in three regions:
• Cutoff : V
GS
<V
TH
, I
D
= 0 (transistor off ).
• T rio de (Linear): V
GS
>V
TH
, V
DS
<V
GS
-V
TH
, I
D
?V
DS
.
• Saturation: V
GS
> V
TH
, V
DS
= V
GS
-V
TH
, I
D
=
1
2
k
n
(V
GS
-V
TH
)
2
(1+?V
DS
) ,
where k
n
=µ
n
C
ox
W
L
, ? is the c hannel-length mo dulation parameter.
2. Biasing T ec hniques
Biasing sets the Q-p oin t in the saturation region for a mplification. Common metho ds for
n-c hannel enhancemen t MOSFET s include:
1. Fixed Bias:
• Gate v oltage V
G
is set b y a v oltage divider or fixed source.
• Drain curren t: I
D
=
1
2
k
n
(V
GS
-V
TH
)
2
.
• Drain-source v oltage: V
DS
=V
DD
-I
D
R
D
, where R
D
is the drain resistor.
• Dra wbac k: Sensitiv e to V
TH
and k
n
v ariations.
2. Self-Bias:
• A resistor R
S
is added b et w een source and ground.
• Gate-source v oltage: V
GS
=V
G
-I
D
R
S
.
• Drain curren t: Solv e I
D
=
1
2
k
n
(V
G
-I
D
R
S
-V
TH
)
2
.
• A dv an tage: Stabilizes I
D
against parameter v ariations.
3. V oltage Divider Bias:
• Resistors R
1
and R
2
form a v oltage divider for gate v oltage: V
G
=V
DD
R
2
R
1
+R
2
.
• Source v oltage: V
S
=I
D
R
S
.
• Gate-source v o ltage: V
GS
=V
G
-V
S
.
• Drain-source v oltage: V
DS
=V
DD
-I
D
(R
D
+R
S
) .
• A dv an tage: High stabilit y against V
TH
and temp erature v ariations.
3. MOSFET Amplifiers
MOSFET s are used in three amplifier configurations:
1
1. Common-Source (CS) Amplifier:
• Input at gate, output a t drain.
• V oltage gain: A
v
=-g
m
R
D
, where g
m
= k
n
(V
GS
-V
TH
) is the transconduc-
tance.
• High input imp edance, m o derate output imp edance.
• Phase in v ersion (180°) .
2. Common-Drain (CD) Amplifier (Source F ollo w er):
• Input at gate, output a t source.
• V oltage gain: A
v
˜
gmR
S
1+gmR
S
< 1 .
• High input imp edance , lo w output imp edance.
• No phase in v ersion.
3. Common-Gate (CG) Amplifier:
• Input at source, output at drain.
• V oltage gain: A
v
˜g
m
R
D
.
• Lo w input imp edanc e, mo derate output imp edance.
• No phase in v ersion.
4. Stabilization
Stabilization minimizes Q-p oin t shifts due to temp erature, V
TH
, or k
n
v ariations:
• Source Resistor (R
S
): Pro vides negativ e feedbac k. IfI
D
increases,V
S
=I
D
R
S
rises,
reducing V
GS
, stabilizing I
D
.
• Constan t Curren t Source: Replaces R
S
for b etter stabilit y .
• T emp erature Comp ensation: Circuits adjust V
G
to coun ter V
TH
c hanges.
5. Key Considerations
• Ensure V
DS
>V
GS
-V
TH
for saturation region op eration.
• Use b ypass capacitors across R
S
to preserv e A C gain.
• Select R
D
and R
S
to set V
DS
˜ 0.5V
DD
for maxim um signal swing.
• A ccoun t for ? in high-precision desig ns for accurate I
D
.
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