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A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.
What is the size of a page in KB in this computer?
- a)2
- b)4
- c)8
- d)16
Correct answer is option 'C'. Can you explain this answer?
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Most Upvoted Answer
A computer uses 46-bit virtual address, 32-bit physical address, and a...
Concept:
To minimize the need for contiguous allocation of physical memory, paging is used.
Logical address space or virtual address space is the set of all logical addresses generated by the program.
Physical addresses are the actual addresses available in memory.
Physical address space is the set of all physical addresses generated by the program.
Mapping of the virtual address to physical address is done by hardware device i.e. Memory Management Unit (MMU) & is called paging technique.
Physical Address space is divided into fixed-size no. of blocks called frames.
The logical address space is divided into fixed-size no. of blocks called pages.
To minimize the need for contiguous allocation of physical memory, paging is used.
Logical address space or virtual address space is the set of all logical addresses generated by the program.
Physical addresses are the actual addresses available in memory.
Physical address space is the set of all physical addresses generated by the program.
Mapping of the virtual address to physical address is done by hardware device i.e. Memory Management Unit (MMU) & is called paging technique.
Physical Address space is divided into fixed-size no. of blocks called frames.
The logical address space is divided into fixed-size no. of blocks called pages.
Calculation:
Page table entry size = 32 bits or 4 Bytes
No. of entries in one page = 2p/4
VAS = 46 bits
Consider size of page = 2p Bytes
Virtual address space (VAS) = No. of entries x page size
No. of entries for one level Page table (PT) = 2p ×4
Therefore, for 3 levels PT
246 x 26 = 24p
252 = 24p
52 = 4p
P = 13
So, the page size is 213 or 8KB.
Hence, the correct answer is “option 3”.
Page table entry size = 32 bits or 4 Bytes
No. of entries in one page = 2p/4
VAS = 46 bits
Consider size of page = 2p Bytes
Virtual address space (VAS) = No. of entries x page size
No. of entries for one level Page table (PT) = 2p ×4
Therefore, for 3 levels PT
246 x 26 = 24p
252 = 24p
52 = 4p
P = 13
So, the page size is 213 or 8KB.
Hence, the correct answer is “option 3”.
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A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?
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A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? for Class 6 2024 is part of Class 6 preparation. The Question and answers have been prepared according to the Class 6 exam syllabus. Information about A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Class 6 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?.
A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? for Class 6 2024 is part of Class 6 preparation. The Question and answers have been prepared according to the Class 6 exam syllabus. Information about A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? covers all topics & solutions for Class 6 2024 Exam. Find important definitions, questions, meanings, examples, exercises and tests below for A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer?.
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ample number of questions to practice A computer uses 46-bit virtual address, 32-bit physical address, and a three-level paged page table organization. The page table base register stores the base address of the first-level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second-level table (T2). Each entry of T2 stores the base address of a page of the third-level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16-way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes.What is the size of a page in KB in this computer?a)2b)4c)8d)16Correct answer is option 'C'. Can you explain this answer? tests, examples and also practice Class 6 tests.
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