The adder component is an 8-bit ripple carry adder; real ALUs would normally feature a 'carry-look-ahead adder', allowing for high-speed operation. However for this example the much simpler ripple carry adder is adequate, as the operation is totally manual.
The adder component is illustrated in Fig. 5.8.5 and consists of eight full-adder circuits with additional logic consisting of an XOR gate to detect overflow errors, and an 8-input NOR gate to detect a zero result.
Negative result are indicated by sampling the most significant bit of the ‘sum’ output, and a ‘carry’ is indicated by sampling the carry output of the most significant full adder.
Four D type flip- flop are used as ‘flag’ outputs to indicate the current state of the ALU after each operation.
This component uses two 4- bit shift register (from Module 5.7) connected in cascade as shown in Fig. 5.8.6. Inputs are provided for clock pulses, (CK), a right/left shift control (R/~L) and an input to control whether the shift register is in shift, or load-enable modes (SHIFT/~LE).
If ~LE is chosen temporarily during shift operations, the shift register can be reloaded from the data placed on the 8-bit ‘Data A’ and ‘carry-in’ (CIN) inputs. This action is synchronised to the CK pulse by the external NAND and NOT gates connecting the SHIFT/~LE input to the two ~LOAD inputs of the 4-bit shift registers.
An additional JKflip- flop (mimicking a D type flip-flop) is placed between the ‘serial-right’ output of the shift register and COUT to allow the ‘clear carry’ input (~CLC) to clear the carry flag.