Asynchronous Counters Video Lecture | Digital Electronics - Electrical Engineering (EE)

asynchronous counters we have seen the
introduction to counters in our previous
tutorial and now we're here to discuss
asynchronous counters as we discussed
earlier a synchronous counter is one in
which each flip-flop is triggered by the
output of the previous flip-flop which
limits the speed of operation
asynchronous counters are also called
ripple counters these counters are
easier to design and are constructed
using minimum hardware
now let's discuss a few examples of
asynchronous counters at first we'll
start with the two-bit asynchronous
counter a two-bit a synchronous counter
circuit is given we have connected the
external clock only to the clock input
of the first flip-flop that is FF 0 here
we have given a bubble at the clock
which indicates that output changes its
state during the negative edge or
falling edge of the clock pulse so FF 0
changes state at the falling edge of
each clock pulse but FF 1 changes only
during the falling edge of the Q output
of FF 0 because of the inherent
propagation delay through a flip-flop we
know that the transition of the input
clock pulse and a transition of the Q
output of FF 0 can never occur at
exactly the same time therefore the
flip-flops cannot be triggered
simultaneously producing an asynchronous
operation you may wonder by seeing this
timing diagram in which the transitions
of Q 0 Q 1 and clock are shown is
simultaneous even though this is an
asynchronous counter but actually there
is some small delay between the clock q0
and q1 transitions usually all the clear
inputs are connected together so that a
single pulse can clear all the
flip-flops before counting starts the
clock pulse which we have given
externally is fed into FF 0 and is
rippled or moved
through the other counters after some
propagation delays like a ripple on the
water
hence the name ripple counter the
two-bit ripple counter circuit which we
discussed now has four states each one
corresponding to account value similarly
a counter with n flip-flops can have two
to the power n states the number of
states in a counter is known as its mod
or modulo number thus a two bit counter
is a mod for counter will discuss these
mod counters in our upcoming tutorials
now let's discuss asynchronous up
counter this is a very simple basic
counter for up counters the transition
will be from high to low here we have
the circuit diagram
waveforms and table are given for your
better understanding
QA output changes for every negative
transition of clock pulse QB output
changes whenever there is a transition
from logic one to logic zero in QA QC
output changes whenever there is a
transition from logic one to logic zero
in QB now let's discuss the asynchronous
down counter this is very similar to the
up counter the only difference is that
for the down counter the transition will
be from low to high here is the circuit
diagram for you
the wave forms and the table are here
QA output changes for every positive
transition of clock pulse QB output
changes whenever there is a transition
from logic zero to logic one in QA QC
output changes whenever there is a
transition from logic zero to logic one
in QB here we have a note to remember an
up counter using n flip-flops counts
upward from a minimum count that is from
0 to 2 to the power n minus 1 and the
down counter using n flip-flops counts
downward from a maximum of 2 to the
power n minus 1 to 0 now let's discuss
the asynchronous up/down counter in
certain applications we may need a
counter that must be able to count both
upwards and downwards now we're going to
discuss such a counter that counts both
up as well as down the circuit given is
a 3 bit up/down counter
it counts up or down depending on the
status of the control signals up and
down when we give the control input up
as one and down as zero the nand network
between F F 0 and F F 1 will give the
non inverted output Q of FF 0 as the
clock input for FF 1 similarly Q of F F
1 will be given through the other NAND
network into the clock input of F F 2
thus the counter will count up when we
give the control input up as 0 and down
as 1 the inverted outputs of F F 0 and F
F 1 that is Q Bar and Q 1 bar are given
as the clock inputs for ff1 and ff2
respectively
if the flip-flops are originally reset
to zeros then the counter will count
downwards as input pulses are applied
here is the table for you which gives
you a clear understanding of how this
counter counts up as well as down from
the circuit it is clear that an
asynchronous up/down counter is slower
than an up counter or a down counter
because of the additional propagation
delay introduced by the nand networks I
hope you're clear about these up/down
counters now we will discuss the
asynchronous Decade counter the binary
counters which we have discussed so far
have 2 to the power n States but
counters with states less than this
number are also possible they are
designed to have the number of states in
their sequences which are called
truncated or reduced sequences these
sequences are achieved by forcing the
counter to recycle before going through
all of its normal states a common
modulus for counters with truncated
sequences is 10 a counter with 10 states
in its sequence is called a decade
counter the circuit given here is an
implementation of the decade counter
once the counter counts to ten that is
one zero one zero all the flip-flops are
being cleared notice that only q1 and q3
are used to decode the count of ten this
is called partial decoding as none of
the other states from zero to nine have
both q1 and q3 high at the same time the
sequence of the decade counter is given
in this table
now I hope you all understand these
asynchronous counters and the various
types of asynchronous counters which we
came across in this tutorial so now
we'll move on to the next lesson which
deals with synchronous counters