Biasing FET | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

BIASING FET:-

        For the proper functioning of a linear FET amplifier, it is necessary to maintain the operating point Q stable in the central portion of the pinch off region. The Q point should be independent of device parameter variations and ambient temperature variations.

This can be achieved by suitably selecting the gate to source voltage V_gs and drain current I_d which is referred to as biasing.

 JFET biasing circuits are very similar to BJT biasing circuits. The main difference between JFET circuits and BJT circuits is the operation of the active components themselves.

There are mainly two types of Biasing circuits

1. Self bias
2. Voltage divider bias.

6.9.1 SELF BIAS

Self bias is a JFET biasing circuit that uses a source resistor to help reverse bias the JFET gate. A  self bias circuit is shown in the fig. Self bias is the most common type of JFET bias. This JFET must be operated such that gate source junction is always reverse biased. This condition requires a negative V_gs for an N-channel JFET and a positive V_gs for P-channel JFET. This can be achieved using the self bias arrangement as shown in Fig. The gate resistor R_G doesn’t affect the bias because it has essentially no voltage drop across it, and the gate remains at 0 V. R_G is necessary only to isolate an ac signal from ground in amplifier applications. The voltage drop across resistor R_S makes gate source junction reverse biased.

For the dc analysis, coupling capacitors are open circuits.

For the N channel FET in Fig (a)

I_S produces a voltage drop across R_S and makes the source positive w.r.t ground. In any JFET circuit all the source current passes through the device to the drain circuit. This is due to the fact that there is no significant gate current.

We can define source current as  I_S = I_D

(V_G =0 because there is no gate current flowing in R_G. So, V_G across R_G is zero)

V_G =0 then V_S= I_SR_S =I_D R_S

V_GS = V_G-V_S =0-I_D R_S=- I_D R_S

DC analysis of self Bias:-

In the following DC analysis, the N-channel JFET shown in the fig. is used for illustration.

For DC analysis we can replace coupling capacitors by open circuits and we can also replace the resistor R_G by a short circuit equivalent.:. I_G = 0.The relation between I_D and V_GS is given by-

             Id=Idss                                    

V_GS for N-channel JFET is =-I_d R_s

Substuting this value in the above equation,

For the N-chanel FET in the above figure

I_s produces a voltage drop across R_s and makes the source positive w.r.t ground in any JFET circuit, all the source current passes through the device to drain circuit this is due to the fact that there is no significant gate current. Therefore, we can define source current as I_s=I_d and V_g=0 then

V_s= I_s R_s =I_dR_s

V_gs=V_g-V_s=0-I_dR_s=-I_dR_s

Drawing the self bias line:-

Typical transfer characteristics for a self biased JFET are shown in the fig.

The maximum drain current is 6mA and the gate source cut off voltage is -3V. This means the gate voltage has to be between 0 and -3V.

Now using the equation V_gs= -I_DR_S and assuming R_S of any suitable value we can draw the self bias line.

Let us assume R_S = 500Ω

 With this Rs , we can plot two points corresponding to I_D = 0 and I_D = I_DSS

      for I_D = 0

V_GS = -I_D R_S

V_GS = 0 x (500.Ω) = 0V

So the first point is (0 ,0)

                                      ( I_D, V_GS)

For I_D= I_DSS=6mA

V_GS = (-6mA) (500 Ω) = -3V

So the 2^nd  Point will be (6mA,-3V)

By plotting these two points, we can draw the straight line through the points. This line will intersect the transconductance curve and it is known as self bias line.The intersection point gives the operating point of the self bias JFET for the circuit.

At Q point , the I_D is slightly  > than 2mA and V_GS is slightly > -1V. The Q point for the self bias JFET depends on the value of R_S. If R_S is large, Q point is far down on the transconductance curve, I_D is small, when R_S is small Q point is far up on the curve , I_D is large.

6.9.2 VOLTAGE DIVIDER BIAS:-

The fig. shows N channel JFET with voltage divider bias. The voltage at the source of JFET must be more positive than the voltage at the gate in order to keep the gate to source junction reverse biased. The source voltage is

V_S = I_DR_S

The gate voltage is set by resistors R1 and R2 as expressed by the following equation using the voltage divider formula.

For dc analysis:

Applying KVL to the input circuit

V_G-V_GS-V_S =0

:: V_GS = V_G-Vs=VG-I_SR_S

V_GS = V_G-I_DR_S       :: I_S = I_D

Applying KVL to the input circuit we get

V_DS+I_DR_D+V_S-V_DD =0

::V_DS = V_DD-I_DR_D-I_DR_S

V_DS = V_DD-I_D ( R_D +R_S )

The Q point of a JFET amplifier , using the voltage divider bias is 

I_DQ  = I_DSS [1-V_GS/V_P]²

V_DSQ = V_DD-I_D ( R_D+R_S )

COMPARISON OF MOSFET WITH JFET

1. In enhancement and depletion types of MOSFET, the transverse electric field induced across an insulating layer deposited on  the semiconductor material controls the conductivity of the channel.
2. In the JFET, the transverse electric field across the reverse biased PN junction controls the conductivity of the channel.
3. The gate leakage current in a MOSFET is of the order of 10^-12A. Hence the input resistance of a MOSFET is very high in the order of 10¹⁰  to  10¹⁵ Ω.  The gate leakage current of a JFET  is of the order of 10^-9A., and its input resistance is of the order of 10⁸Ω.
4. The output characteristics of the JFET are flatter than those of the MOSFET, and hence the drain resistance of a JFET (0.1 to 1MΩ)  is  much higher than that of a MOSFET (1 to 50kΩ).
5. JFETs are operated only in the depletion mode. The depletion type MOSFET may be operated in both depletion and enhancement mode.
6. Comparing to JFET, MOSFETs  are easier to fabricate.
7. Special digital CMOS circuits are available which involve near zero power dissipation and very low voltage and current requirements. This makes them suitable for portable systems.