Computer Science Engineering (CSE)  >  Embedded Systems (Web)  >  Boundary Scan Methods & Standards - 1

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Document Description: Boundary Scan Methods & Standards - 1 for Computer Science Engineering (CSE) 2022 is part of Embedded Systems (Web) preparation. The notes and questions for Boundary Scan Methods & Standards - 1 have been prepared according to the Computer Science Engineering (CSE) exam syllabus. Information about Boundary Scan Methods & Standards - 1 covers topics like and Boundary Scan Methods & Standards - 1 Example, for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises and tests below for Boundary Scan Methods & Standards - 1.

Introduction of Boundary Scan Methods & Standards - 1 in English is available as part of our Embedded Systems (Web) for Computer Science Engineering (CSE) & Boundary Scan Methods & Standards - 1 in Hindi for Embedded Systems (Web) course. Download more important topics related with notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Computer Science Engineering (CSE): Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)
1 Crore+ students have signed up on EduRev. Have you?

Boundary Scan History and Family

Boundary Scan is a family of test methodologies aiming at resolving many test problems: from chip level to system level, from logic cores to interconnects between cores, and from digital circuits to analog or mixed-mode circuits. It is now widely accepted in industry and has been considered as an industry standard in most large IC system designs. Boundary-scan, as defined by the IEEE Std. 1149.1 standard [1-3], is an integrated method for testing interconnects on printed circuit board that is implemented at the IC level. Earlier, most Printed Circuit Board (PCB) testing was done using bed-of-nail in-circuit test equipment. Recent advances with VLSI technology now enable microprocessors and Application Specific Integrated Circuits (ASICs) to be packaged into fine pitch, high count packages. The miniaturization of device packaging, the development of surface-mounted packaging, double-sided and multi-layer board to accommodate the extra interconnects between the increased density of devices on the board reduces the physical accessibility of test points for traditional bed-of-nails in-circuit tester and poses a great challenge to test manufacturing defects in future.

The long-term solution to this reduction in physical probe access was to consider building the access inside the device i.e. a boundary scan register. In 1985, a group of European companies formed Joint European Test Action Group (JETAG) and by 1988 the Joint Test Action Group (JTAG) was formed by several companies to tackle these challenges. The JTAG has developed a specification for boundary-scan testing that was standardized in 1990 by IEEE as the IEEE Std. 1149.1-1990. In 1993 a new revision to the IEEE Std. 1149.1 standard was introduced (1149.1a) and it contained many clarifications, corrections, and enhancements. In 1994, a supplement that contains a description of the boundary-scan Description Language (BSDL) was added to the standard. Since that time, this standard has been adopted by major electronics companies all over the world. Applications are found in high volume, high-end consumer products, telecommunication products, defense systems, computers, peripherals, and avionics. Now, due to its economic advantages, smaller companies that cannot afford expensive in-circuit testers are using boundary-scan. Figure 41.1 gives an overview of the boundary scan family, now known as the IEEE 1149.x standards.

NumberDescriptionYear
IEEE 1149.1Testing of digital chips and interconnections between chipsStd 1149.1 – 1990
IEEE 1149.1aAdded supplement A. Rewrite of the chapter describing boundary registerStd 1149.1a – 1993
IEEE 1149.1bSupplement B - formal description of the boundary-scan Description Language (BSDL)Std 1149.1b – 1994
IEEE 1149.1cCorrections, clarifications and enhancements of IEEE Std 1149.1a and Std 1149.1b. Combines 1149.1a & 1149.1bStd 1149.1 –2001
IEEE 1149.2Extended Digital Serial Interface. It has merged with 1149.1 group.Obsolete
IEEE 1149.3Direct Access Testability InterfaceObsolete
IEEE 1149.4Test Mixed-Signal and Analog assembliesStd. 1149.4 – 1999
IEEE 1149.5Standard Module Test and Maintenance (MTM) Bus Protocol. Deals with test at system level, 1149.2 has merged with.Std. 1149.5 –1995
IEEE 1149.6Includes AC-coupled and/or differential nets.Std 1149.6 - 2002
IEEE 1532It is a derivative standard for in-system programming (ISP) of digital devices.2000

Fig. 41.1 IEEE 1149 Family

The Std. 1149.1, usually referred to as the digital boundary scan, is the one that has been used widely. It can be divided into two parts: 1149.1a, or the digital Boundary Scan Standard, and 1149.1b, or the Boundary Scan Description Language (BSDL) [1,6]. Std. 1149.1 defines the chip level test architecture for digital circuits, and Std. 1149.1b is a hardware description language used to describe boundary scan architecture. The 1149.2 defines the extended digital series interface in the chip level. It has merged with 1149.1 group. The 1149.3 defines the direct access interface in contrast to 1149.2. Unfortunately this work has been discontinued. 1149.4 IEEE Standard deals with Mixed-Signal Test Bus [4]. This standard extends the test structure defined in IEEE Std. 1149.1 to allow testing and measurement of mixed-signal circuits. The standard describes the architecture and the means of control and access to analog and digital test data. The Std.1149.5 defines the bus protocol at the module level. By combining this level and Std.1149.1a one can easily carry out the testing of a PC board.

1149.6 IEEE Standard for Boundary-Scan Testing of Advanced Digital Networks is released in 2002. This standard augments 1149.1 for the testing of conventional digital networks and 1149.4 for analog networks. The 1149.6 standard defines boundary-scan structures and methods required to test advanced digital networks that are not fully covered by IEEE Std. 1149.1, such as networks that are AC-coupled, differential, or both.

This extension of 1149.1 standardizes programming access and methodology for programmable integrated circuit devices. Devices such as CPLDs and FPGAs, regardless of vendor, that implement this standard may be configured (written), read back, erased and verified, singly or concurrently, with a standardized set of resources based upon the algorithm description contained in the 1532 BSDL file. JTAG Technologies programming tools contain support for 1532-compliant devices and automatically generate the applications. Clearly the testing of mixed-mode circuits at the various levels of integration will be a critical test issue for the system-on-chip design. Therefore there is a demand to combine all the boundary scan standards into an integrated one.

Boundary Scan Architecture

The boundary-scan test architecture provides a means to test interconnects between integrated circuits on a board without using physical test probes. It adds a boundary-scan cell that includes a multiplexer and latches, to each pin on the device. Figure 41.2 [1] illustrates the main elements of a universal boundary-scan device.

The Figure 41.2 shows the following elements:

  • Test Access Port (TAP) with a set of four dedicated test pins: Test Data In (TDI), Test Mode Select (TMS), Test Clock (TCK), Test Data Out (TDO) and one optional test pin Test Reset (TRST*).
  • A boundary-scan cell on each device primary input and primary output pin, connected internally to form a serial boundary-scan register (Boundary Scan).
  • A TAP controller with inputs TCK, TMS, and TRST*.
  • An n-bit (n >= 2) instruction register holding the current instruction.
  • A 1-bit Bypass register (Bypass).
  • An optional 32-bit Identification register capable of being loaded with a permanent device identification code.

1149.1 Chip Architecture 

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.2 Main Elements of a IEEE 1149.1 Device Architecture

The test access ports (TAP), which define the bus protocol of boundary scan, are the additional I/O pins needed for each chip employing Std.1149.1a. The TAP controller is a 16-state final state machine that controls each step of the operations of boundary scan. Each instruction to be carried out by the boundary scan architecture is stored in the Instruction Register. The various control signals associated with the instruction are then provided by a decoder. Several Test Data Registers are used to stored test data or some system related information such as the chip ID, company name, etc.

Bus Protocol

The Test Access Ports (TAPs) are genral purpose ports and provide access to the test function of the IC between the application circuit and the chip’s I/O pads. It includes four mandatory pins TCK, TDI, TDO and TMS and one optional pin TRST* as described below. All TAP inputs and outputs shall be dedicated connections to the component (i.e., the pins used shall not be used for any other purpose).

  • Test Clock Input (TCK): a clock independent of the system clock for the chip so that test operations can be synchronized between the various parts of a chip. It also synchronizes the operations between the various chips on a printed circuit board. As a convention, the test instructions and data are loaded from system input pins on the rising edge of TCK and driven through system output pins on its falling edge. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency (up to a maximum of some MHz). It can be even pulsed at varying rates.
  • Test Data Input (TDI): an input line to allow the test instruction and test data to be loaded into the instruction register and the various test data registers, respectively.
  • Test Data Output (TDO): an output line used to serially output the data from the JTAG registers to the equipment controlling the test.
  • Test Mode Selector (TMS): the test control input to the TAP controller. It controls the transitions of the test interface state machine. The test operations are controlled by the sequence of 1s and 0s applied to this input. Usually this is the most important input that has to be controlled by external testers or the on-board test controller.

Test Reset Input (TRST*): The optional TRST* pin is used to initialize the TAP controller, that is, if the TRST* pin is used, then the TAP controller can be asynchronously reset to a TestLogic-Reset state when a 0 is applied at TRST*. This pin can also be used to reset the circuit under test, however it is not recommended for this application.

Boundary Scan Cell 

The IEEE Std. 1149.1a specifies the design of four test data registers as shown in Figure 41.2. Two mandatory test data registers, the bypass and the boundary-scan resisters, must be included in any boundary scan architecture. The boundary scan register, though may be a little confusing by its name, refers to the collection of the boundary scan cells. The other registers, such as the device identification register and the design-specific test data registers, can be added optionally.

Basic Boundary – Scan Cell (BC 1)

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.3 Basic Boundary Scan Cell

Figure 41.3 [1] shows a basic universal boundary-scan cell, known as a BC_1. The cell has four modes of operation: normal, update, capture, and serial shift. The memory elements are two Dtype flip-flops with front-end and back-end multiplexing of data. It is important to note that the circuit shown in Figure 41.3 is only an example of how the requirement defined in the Standard could be realized. The IEEE 1149.1 Standard does not mandate the design of the circuit, only its functional specification. The four modes of operation are as follows:

  1. During normal mode also called serial mode, Data_In is passed straight through to Data_Out.
  2. During update mode, the content of the Update Hold cell is passed through to Data_Out. Signal values already present in the output scan cells to be passed out through the device output pins. Signal values already present in the input scan cells will be passed into the internal logic.
  3. During capture mode, the Data_In signal is routed to the input Capture Scan cell and the value is captured by the next ClockDR. ClockDR is a derivative of TCK. Signal values on device input pins to be loaded into input cells, and signal values passing from the internal logic to device output pins to be loaded into output cells
  4. During shift mode, the Scan_Out of one Capture Scan cell is passed to the Scan_In of the next Capture Scan cell via a hard-wired path.

The Test ClocK, TCK, is fed in via yet another dedicated device input pin and the various modes of operation are controlled by a dedicated Test Mode Select (TMS) serial control signal. Note that both capture and shift operations do not interfere with the normal passing of data from the parallel-in terminal to the parallel-out terminal. This allows on the fly capture of operational values and the shifting out of these values for inspection without interference. This application of the boundary-scan register has tremendous potential for real-time monitoring of the operational status of a system — a sort of electronic camera taking snapshots — and is one reason why TCK is kept separate from any system clocks.

Boundary Scan Path 

At the device level, the boundary-scan elements contribute nothing to the functionality of the internal logic. In fact, the boundary-scan path is independent of the function of the device. The value of the scan path is at the board level as shown in Figure 41.4 [1]. The figure shows a board containing four boundary-scan devices. It is seen that there is an edgeconnector input called TDI connected to the TDI of the first device. TDO from the first device is permanently connected to TDI of the second device, and so on, creating a global serial scan path terminating at the edge connector output called TDO. TCK is connected in parallel to each device TCK input. TMS is connected in parallel to each device TMS input. All cell boundary data registers are serially loaded and read from this single chain.

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.4 MCM with Serial Boundary Scan Chain

The advantage of this configuration is that only two pins on the PCB/MCM are needed for boundary scan data register support. The disadvantage is very long shifting sequences to deliver test patterns to each component, and to shift out test responses. This leads to expensive time on the external tester. As shown in Figure 41.5 [1], the single scan chain is broken into two parallel boundary scan chains, which share a common test clock (TCK). The extra pin overhead is one more pin. As there are two boundary scan chains, so the test patterns are half as long and test time is roughly halved. Here both chains share common TDI and TDO pins, so when the top two chips are being shifted, the bottom two chips must be disabled so that they do not drive their TDO lines. The opposite must hold true when the bottom two chips are being tested.

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.5 MCM with two parallel boundary scan chains

TAP Controller

The operation of the test interface is controlled by the Test Access Port (TAP) controller. This is a 16-state finite state-machine whose state transitions are controller by the TMS signal; the statetransition diagram is shown in Figure 41.7. The TAP controller can change state only at the rising edge of TCK and the next state is determined by the logic level of TMS. In other words, the state transition in Figure 41.6 follows the edge with label 1 when the TMS line is set to 1, otherwise the edge with label 0 is followed. The output signals of the TAP controller corresponding to a subset of the labels associated with the various states. As shown in Figure 41.2, the TAP consists of four mandatory terminals plus one optional terminal. The main functions of the TAP controller are:

  • To reset the boundary scan architecture,
  • To select the output of instruction or test data to shift out to TDO,
  • To provide control signals to load instructions into Instruction Register,
  • To provide signals to shift test data from TDI and test response to TDO, and
  • To provide signals to perform test functions such as capture and application of test data.

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.6 Top level view of TAP Controller 

Figure 41.6 shows a top-level view of TAP Controller. TMS and TCK (and the optional TRST*) go to a 16-state finite-state machine controller, which produces the various control signals. These signals include dedicated signals to the Instruction register (ClockIR, ShiftIR, UpdateIR) and generic signals to all data registers (ClockDR, ShiftDR, UpdateDR). The data register that actually responds is the one enabled by the conditional control signals generated at the parallel outputs of the Instruction register, according to the particular instruction.

The other signals, Reset, Select and Enable are distributed as follows:

  • Reset is distributed to the Instruction register and to the target Data Register
  • Select is distributed to the output multiplexer
  • Enable is distributed to the output driver amplifier

It must be noted that the Standard uses the term Data Register to mean any target register except the Instruction register

TAP Controller State Diagram 

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

Fig. 41.7 State transition diagram of TAP controller

Figure 41.7 shows the 16-state state table for the TAP controller. The value on the state transition arcs is the value of TMS. A state transition occurs on the positive edge of TCK and the controller output values change on the negative edge of TCK. The 16 states can be divided into three parts. The first part contains the reset and idle states, the second and third parts control the operations of the data and instruction registers, respectively. Since the only difference between the second and the third parts are on the registers they deal with, in the following only the states in the first and second parts are described. Similar description on the second part can be applied to the third part.

  1. Test-Logic-Reset: In this state, the boundary scan circuitry is disabled and the system is in its normal function. Whenever a Reset* signal is applied to the BS circuit, it also goes back to this state. One should also notice that whatever state the TAP controller is at, it will goes back to this state if 5 consecutive 1's are applied through TMS to the TAP controller.
  2. Run-Test/Idle: This is a state at which the boundary scan circuitry is waiting for some test operations such as BIST operations to complete. One typical example is that if a BIST operation requires 216 cycles to complete, then after setting up the initial condition for the BIST operation, the TAP controller will go back to this state and wait for 216 cycles before it starts to shift out the test results.
  3. Select-DR-Scan: This is a temporary state to allow the test data sequence for the selected test-data register to be initiated.
  4. Capture-DR: In this state, data can be loaded in parallel to the data registers selected by the current instruction.
  5. Shift-DR: In this state, test data are scanned in series through the data registers selected by the current instruction. The TAP controller may stay at this state as long as TMS=0. For each clock cycle, one data bit is shifted into (out of) the selected data register through TDI (TDO).
  6. Exit-DR: All parallel-loaded (from the Capture-DR state) or shifted (from the Shift-DR state) data are held in the selected data register in this state.
  7. Pause-DR: The BS pauses its function here to wait for some external operations. For example, when a long test data is to be loaded to the chip(s) under test, the external tester may need to reload the data from time to time. The Pause-DR is a state that allows the boundary scan architecture to wait for more data to shift in.
  8. Exit2-DR: This state represents the end of the Pause-DR operation, allows the TAP controller to go back to ShiftDR state for more data to shift in.
  9. Update-DR: The test data stored in the first stage of boundary scan cells is loaded to the second stage in this state.
The document Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE) is a part of the Computer Science Engineering (CSE) Course Embedded Systems (Web).
All you need of Computer Science Engineering (CSE) at this link: Computer Science Engineering (CSE)

Related Searches

Summary

,

pdf

,

past year papers

,

Important questions

,

shortcuts and tricks

,

MCQs

,

Free

,

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

,

practice quizzes

,

Previous Year Questions with Solutions

,

study material

,

ppt

,

Semester Notes

,

video lectures

,

Viva Questions

,

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

,

Exam

,

Boundary Scan Methods & Standards - 1 Notes | Study Embedded Systems (Web) - Computer Science Engineering (CSE)

,

mock tests for examination

,

Sample Paper

,

Objective type Questions

,

Extra Questions

;