The document CMOS Inverter Characteristics Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course VLSI System Design.

All you need of Electrical Engineering (EE) at this link: Electrical Engineering (EE)

**Objectives**

In this lecture you will learn the following

- CMOS Inverter Characterisitcs
- Noise Margins
- Regions of operation
- Beta-n by Beta-p ratio

**15. CMOS Inverter Characterisitcs**

The complementry CMOS inverter is realized by the series connection of a p- and n-device as in fig 15.11.

**Fig 15.11: CMOS Inverter**

**Inverter characteristics:**

In the below graphical representation(fig.2.) The **I-V** characteristics of the p-device is reflected about x-axis. This step is followed by taking the absolute values of the p-device, Vds and superimposing the two characteristics. Solving Vinn and Vinp and Idsn = Idsp gives the desired transfer characteristics of a CMOS inverter as in fig3.

**15.2 Noise Margins**

Noise margin is a parameter closely related to the input-output voltage characteristics. This parameter allows us to determine the allowable noise voltage on the input of a gate so that the output will not be affected. The specification most commonly

used to specify noise margin (or noise immunity) is in terms of two parameters- The LOW noise margin, NML, and the HIGH noised margin, NMH. With reference to Fig 4. NML is defined as the difference in magnitude between the maximum LOW output

voltage of the driving gate and the maximum input LOW voltage recognized by the driven gate. Thus,

**Fig 15.2: Noise Margin diagram**

The value of NMH is difference in magnitude between the minimum HIHG output voltage of the driving gate and the minimum input HIGH voltage recognized by the receiving gate. Thus,

Where,

V_{IHmin} = minimum HIGH input voltage

V_{ILmax }= maximum LOW input voltage

V_{OHmin }= minimum HIGH output voltage

V_{OLmax }= maximum LOW output voltage.

**15.3: Regions of Operation**

The operation of CMOS inverter can be divided into five regions .The behavior of **n-** and **p-**devices in each of region may be found using

We will describe about each regions in details-

**Region A :** This region is defined by **0 =< V _{in} < V_{tn}** in which the n-device is cut off (I

**Region B :** This region is characterized by V** _{tn }=< V_{in }< V_{DD} _{/2}** in which the p-device is in its nonsaturated region (V

and V_{tn} =threshold voltage of n-device, µ_{n}=mobility of electrons W_{n }= channel width of n-device &** L _{n}** = channel length of n-device

**Fig 15.31: Equivalent circuit of MOSFET in region B**

The current for the p-device can be obtained by noting that V** _{gs} =( V_{in} – V_{DD })** and V

and V_{tp} =threshold voltage of n-device, µ_{p}=mobility of electrons, W_{p} = channel width of n-device & L_{p }= channel length of n-device. The output voltage V**out **can be expressed as-

**Region C:** In this region both the n- and p-devices are in saturation. This is represented by fig 7 which shows two current

**Fig 15 .32: Equivalent circuit of MOSFET in region C**

This yields,

By setting,

Which implies that region C exists only for one value of V_{in}. We have assumed that a MOS device in saturation behaves like an ideal current soured with drain-to-source current being independent of V_{ds}.In reality, as V_{ds} increases, I_{ds} also increases slightly; thus region C has a finite slope. The significant factor to be noted is that in region C, we have two current sources in series, which is an “unstable” condition.

Thus a small input voltage as a large effect at the output. This makes the output transition very steep, which contrasts with the equivalent nMOS inverter characteritics. characteritics. The above

expression of V_{th} is particularly useful since it provides the basis for defining the gate threshold V_{inv} which corresponds to the state where Vout=V_{in} .This region also defines the “gain” of the CMOS inverter when used as a small signal amplifier.

**Fig 15.33: Equivalent circuit of MOSFET in region D**

**Region D:** This region is described by V_{DD/2 }<V_{in} =< V_{DD}+ V_{tp}.The p-device is in saturation while the n-device is operation in its nonsaturated region. This condition is represented by the equivalent circuit shown in fig 15.33 .The two currents may be written as

with I_{dsn} = -I_{dsp}.

The output voltage becomes

**Region E:** This region is defined by the input condition V** _{in} >= V_{DD} -V_{tp}**, in which the pdevice is cut off (I

From the transfer curve , it may be seen that the transition between the two states is very step.This characteristic is very desirable because the noise immunity is maximized.

**15.4 β _{n}**/

**Figure 15.4: β _{n}/β_{p graph}**

The gate-threshold voltage, V_{inv}, where V** _{in }=V_{out}** is dependent on

Offer running on EduRev: __Apply code STAYHOME200__ to get INR 200 off on our premium plan EduRev Infinity!

35 docs|28 tests

### Propagation Delay Calculation of CMOS Inverter - Electronics & Communication Engineering

- Doc | 3 pages
### Pseudo NMOS Inverter (Part - 1)

- Doc | 2 pages
### Pseudo NMOS Inverter (Part - 2)

- Doc | 1 pages
### Pseudo NMOS Inverter (Part - 3)

- Doc | 1 pages
### Analyzing Delay for Various Logic Circuits

- Doc | 5 pages

- Test: Propagation Delays
- Test | 10 ques | 10 min
- Test: Inverter Delays
- Test | 10 ques | 10 min