BJT and FET
TRANSISTOR (BJT/FET) BIASING AND STABILIZATION
The transistor is biased (with the help of external voltage in such a manner so the Q-point is selected in the middle portion the transistor output characteristic.
When the ac voltage is superimposed it is ensure that the positive and negative half of input voltage cycle remain in the linear or active region in the transistor characteristic. Under these condition the transistor output voltage is undistorted.
Once the 0-point has been fixed due to some biasing arrangement it has to be stabilized against the variation in:
(a) Temperature (T) - Ico double for every 10 degree rise in temperature.
(b) IB (Depends on Vbe), i.e. Vbe decrease at the rate of 2.5 mv/degree.
Change in Temperature
In Si transistor. Ico, is of the order of nano amperes compared to milliamps in Ge and so thermal runway and instability is more problem in Ge transistor.
the merit of a biasing circuit in holding the dc collector current Ic at the operating Q-point may be examine by stability factor
I < S < 1 + b.
IC = bIb+(1 +b)Ico....general expression Differentiate with respect to IC.
a) Better than fixed biased circuit.
b) bRc >> Rb as this will give very small value as stability as near to 1.
Drawback of Collector to Base Bias
Self-Bias/Potential divider/Emitter Bias
where S2: Stability (S) at b = b2.
Total increment in Ic is the sum of all three increments due to Ico, b , and Vbe.
And IB =I – Io
From collector current expression
Ic = b Ib + (1 + b) Ico = b Io + (1 + b) Ico
= bI – b Io+ b ICo if b >> and Io of diode and Ico of transistor track each other over the desired temperature rang, then Ico remains essntially constant.
Reverse saturation current Io flows through the diode. If Ico increases due to temperature, the increased current flows through diode decreasing Ib keeping Ib constant.
Thermistors are temperature sensitive element, which has a negative temperature coefficient of resistance.
The thermistor element is placed parallel to and across Vcc and E. R2 of potential divider bias. Increase of temperature reduces resistance and decrease the forward bias reduces Ib and Ic.
Sensistor Compensation It may be placed either in parallel with R1 or parallel with RE. It can also placed in place of RE rather than in parallel with RE.
FET Biasing For the field-effect transistor, the relationship between input and output quantities is nonlinear due to the squared term in Shockley’s equation. The nonlinear relationship between ID and VGS can complicated the mathematical approach to the dc analysis of FET configurations. A graphical approach may limit solutions to tenths-place accuracy, but it is a quicker method for most FET amplifiers.
Another distinct difference between the analysis of BJT and FET transistors is that the input controlling variable for a BJT transistor is a current level, while for the FET a voltage is the controlling variable. In both cases, however, the controlled variable on the
output side is a current level that also defines the important voltage levels of the output circuit.
The general relationships that can be applied to the analysis of all FET amplifiers are IG @ OA and ID =
Is For JEETS and depletion-type MOSFETs, Shockley’s equation is applied to re-late the input and output quantities:
For Enhancement MOSFET ID = k (VGS – Vr)2
It is particularly important to realize that of the equations above are for the device only! They do not change with each network configurations. So long as the device is in the active region.
Table FET Bias Configurations