DC Biasing BJTs (Part - 2) - Electrical Engineering (EE) PDF Download

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Improved bias stability

• Addition of emitter resistance makes the dc bias currents and voltages remain closer to their set value even with variation in – transistor beta – temperature

Stability

In a fixed bias circuit, IB does not vary with b and therefore whenever there is an increase in b, I_C increases proportionately, and thus V_CE reduces making the Q point to drift towards saturation.In an emitter bias circuit, As b increases, IB reduces, maintaining almost same I_C and V_CE thus stabilizing the Q point against b variations.

Saturation current

In saturation V_CE is almost 0V, thus
V_CC = I_C ( R_C + RE )
Thus, saturation current
I_C,_sat = V_CC / ( R_C + R_E )

Load line analysis

The two extreme points on the load line of an emitter bias circuit are,

(0, V_CC / [ R_C + R_E ]) on the Y axis, and ( V_CC, 0) on the X axis.

Voltage divider bias

This is the biasing circuit wherein, I_CQ and V_CEQ are almost independent of b.
The level of I_BQ will change with β so as to maintain the values of I_CQ and V_CEQ almost same, thus maintaining the stability of Q point.
Two methods of analyzing a voltage divider bias circuit are:

Exact method – can be applied to any voltage divider circuit

Approximate method – direct method, saves time and energy, can be applied in most of the circuits.

Exact method

In this method, the Thevenin equivalent network for the network to the left of the base terminal to be found.

To find Rth:

From the above circuit,

R_th = R1| | R2

= R1 R2 / (R1 + R2)

To find Eth

From the above circuit,

E_th = V_R2 = R₂V_CC / (R₁ + R₂)

In the above network, applying KVL

( E_th – V_BE) = I_B [ R_th +( β + 1) R_E ]

I_B = ( E_th – V_BE) / [ R_th +( β + 1) R_E ]

Analysis of Output loop 

KVL to the output loop:
V_CC = I_CR_C + V_CE + I_ER_E
I_E ≌ I_C
Thus, V_CE = V_CC – I_C (R_C + R_E)

Note that this is similar to emitter bias circuit.

Problem

For the circuit given below, find I_C and V_CE.
Given the values of R₁, R₂, R_C, R_E and β = 140 and V_CC = 18V.
For the purpose of DC analysis, all the capacitors in the amplifier circuit are opened.

Solution

Considering exact analysis:

1. Let us find R_th = R₁| | R₂
= R₁ R₂ / (R₁ + R₂) = 3.55K

2. Then find E_th = VR₂ = R₂V_CC / (R₁ + R₂) = 1.64V

3. Then find I_B
I_B = ( E_th – V_BE) / [ R_th +( β + 1) R_E ] = 4.37mA

4. Then find I_C = b I_B = 0.612mA

5. Then find V_CE = V_CC – I_C (R_C + R_E) = 12.63V

Approximate analysis:

The input section of the voltage divider configuration can be represented by the network shown in the next slide.

Input Network

The emitter resistance R_E is seen as (β+1)R_E at the input loop.
If this resistance is much higher compared to R₂, then the current I_B is much smaller than I₂ through R₂.
This means, R_i >> R₂
OR
(β+1)R_E ≥10R2
OR
bR_E ≥ 10R₂
This makes I_B to be negligible.
Thus I₁ through R₁ is almost same as the current I₂ through R₂.
Thus R₁ and R₂ can be considered as in series.
Voltage divider can be applied to find the voltage across R₂ ( V_B) V_B = V_CCR₂ / ( R₁ + R₂)
Once V_B is determined, V_E is calculated as, V_E = V_B – V_BE
After finding V_E, I_E is calculated as, I_E = V_E / R_E
I_E ≌ I_C
V_CE = V_CC – I_C ( R_C + R,)

Problem 

Given: V_CC = 18V, R₁ = 39k Ω, R₂ = 3.9k W, R_C = 4k Ω, R_E = 1.5k Ω and β = 140.
Analyse the circuit using approximate technique.
In order to check whether approximate technique can be used, we need to verify the condition,
βR_E ≥ 10R₂
Here,
βR_E = 210 kΩ and 10R₂ = 39 kΩ
Thus the condition
βR_E ≥ 10R₂ satisfied
Solution

• Thus approximate technique can be applied.
  1. Find V_B = V_CCR₂ / ( R₁ + R₂) = 1.64V
  2. Find V_E = V_B – 0.7 = 0.94V
  3. Find I_E = V_E / R_E = 0.63mA = I_C 
  4. Find V_CE = V_CC – I_C(R_C + R_E) = 12.55V 

Comparison

Both the methods result in the same values for I_C and V_CE since the condition bR_E ≥ 10R₂ is satisfied.
It can be shown that the results due to exact analysis and approximate analysis have more deviation if the above mentioned condition is not satisfied.
For load line analysis of voltage divider network, I_c,max = V_CC/ ( R_C+R_E) when V_CE = 0V and V_CE max = V_CC when I_C = 0.

DC bias with voltage feedback

Input loop

Applying KVL for Input Loop: V_CC = I_C1R_C + I_BR_B + V_BE + I_ER_E

Substituting for IE as (β +1)I_B and solving for I_B, I_B = ( V_CC – V_BE) / [ R_B + β( R_C + R_E)]

Output loop

Neglecting the base current, KVL to the output loop results in,

V_CE = V_CC – I_C ( R_C + R_E)

DC bias with voltage feedback

Input loop

Applying KVL to input loop:

V_CC = I_C^|R_C + I_BR_B + V_BE + I_ER_E
I_C^|≌ I_C and I_C ≌ I_E
Substituting for I_E as (β +1)I_B [ or as βI_B] and solving for
I_B, I_B = ( V_CC - V_BE) / [ R_B + β( R_C + R_E)]

Output loop

Neglecting the base current, and applying KVL to the output loop results in,

V_CE = V_CC – I_C ( R_C + R_E)

In this circuit, improved stability is obtained by introducing a feedback path from collector to base.

Sensitivity of Q point to changes in beta or temperature variations is normally less than that encountered for the fixed bias or emitter biased configurations.

Problem: Given: V_CC = 10V, R_C = 4.7k, R_B = 250W and R_E = 1.2k. b = 90.

Analyze the circuit.

I_B = ( V_CC – V_BE) / [ R_B + β( R_C + R_E)]
=  11.91mA

I_C = (b I_B ) = 1.07mA V_CE = V_CC – I_C ( R_C + R_E)  = 3.69V

In the above circuit, Analyze the circuit if b = 135 ( 50% increase).

With the same procedure as followed in the previous problem, we get  

• I_B = 8.89mA  
• I_C = 1.2mA
• V_CE = 2.92V  

50% increase in b resulted in 12.1% increase in I_C and 20.9% decrease in V_CEQ

Problem 2:

Determine the DC level of IB and VC for the network shown:

Solution: 

Open all the capacitors for DC analysis.
R_B = 91 kΩ + 110 kΩ = 201k I_B = ( V_CC – V_BE) / [ R_B + β( R_C + R_E)]
= (18 – 0.7) / [ 201k + 75( 3.3+0.51)] = 35.5mA 
I_C = β I_B = 2.66mA V_CE = V_CC – (I_CR_C)
= 18 – ( 2.66mA)(3.3k) = 9.22V 

Load line analysis 

The two extreme points of the load line I_C,max and V_CE, max are found in the same as a voltage divider circuit.
I_C,_max = V_CC / (R_C + R_E) – Saturation current
V_CE, _max – Cut off voltage