Formula Sheets: Junction Field Effect Transistors | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

 Page 1


Formula Sheet for Junction Field-E?ect Transistors
(Analog and Digital Electronics) – GATE
1. Basic Concepts
• JFET Types: N-channel, P-channel.
• Structure: Gate, Drain, Source; channel controlled by gate-source voltage.
• Operation: Voltage-controlleddevice, depletion-modeonly(conductsatV
GS
= 0).
• Operating Regions: Ohmic (Linear), Saturation (Pinch-o?), Cut-o?.
2. JFET Characteristics
• Drain Current (Saturation Region, N-channel):
I
D
=I
DSS
(
1-
V
GS
V
P
)
2
where:
– I
DSS
: Drain current when V
GS
= 0.
– V
P
: Pinch-o? voltage (negative for N-channel).
– V
GS
: Gate-source voltage.
• Ohmic Region:
I
D
=
2I
DSS
|V
P
|
2
[
(V
GS
-V
P
)V
DS
-
V
2
DS
2
]
• Cut-o? Region: V
GS
=V
P
, I
D
= 0.
3. Operating Regions
• Cut-o?: V
GS
=V
P
, I
D
= 0.
• Ohmic (Linear): V
GS
>V
P
, V
DS
<V
GS
-V
P
.
• Saturation (Pinch-o?): V
GS
>V
P
, V
DS
=V
GS
-V
P
.
4. Small-Signal Parameters
• Transconductance:
g
m
=
2I
DSS
|V
P
|
(
1-
V
GS
V
P
)
=
v
2I
DSS
I
D
|V
P
|
• Drain Resistance:
r
d
=
?V
DS
?I
D
˜
1
?I
D
where ?: Channel-length modulation parameter (often small for JFETs).
• Input Resistance: R
in
˜8 (gate-source junction reverse-biased).
1
Page 2


Formula Sheet for Junction Field-E?ect Transistors
(Analog and Digital Electronics) – GATE
1. Basic Concepts
• JFET Types: N-channel, P-channel.
• Structure: Gate, Drain, Source; channel controlled by gate-source voltage.
• Operation: Voltage-controlleddevice, depletion-modeonly(conductsatV
GS
= 0).
• Operating Regions: Ohmic (Linear), Saturation (Pinch-o?), Cut-o?.
2. JFET Characteristics
• Drain Current (Saturation Region, N-channel):
I
D
=I
DSS
(
1-
V
GS
V
P
)
2
where:
– I
DSS
: Drain current when V
GS
= 0.
– V
P
: Pinch-o? voltage (negative for N-channel).
– V
GS
: Gate-source voltage.
• Ohmic Region:
I
D
=
2I
DSS
|V
P
|
2
[
(V
GS
-V
P
)V
DS
-
V
2
DS
2
]
• Cut-o? Region: V
GS
=V
P
, I
D
= 0.
3. Operating Regions
• Cut-o?: V
GS
=V
P
, I
D
= 0.
• Ohmic (Linear): V
GS
>V
P
, V
DS
<V
GS
-V
P
.
• Saturation (Pinch-o?): V
GS
>V
P
, V
DS
=V
GS
-V
P
.
4. Small-Signal Parameters
• Transconductance:
g
m
=
2I
DSS
|V
P
|
(
1-
V
GS
V
P
)
=
v
2I
DSS
I
D
|V
P
|
• Drain Resistance:
r
d
=
?V
DS
?I
D
˜
1
?I
D
where ?: Channel-length modulation parameter (often small for JFETs).
• Input Resistance: R
in
˜8 (gate-source junction reverse-biased).
1
5. JFET Biasing
• Self-Bias:
V
GS
=-I
D
R
S
I
D
=I
DSS
(
1+
I
D
R
S
V
P
)
2
• Voltage Divider Bias:
V
G
=V
DD
·
R
2
R
1
+R
2
V
GS
=V
G
-I
D
R
S
• Drain-Source Voltage:
V
DS
=V
DD
-I
D
(R
D
+R
S
)
6. JFET as a Switch
• Cut-o?: Open switch (V
GS
=V
P
, I
D
= 0).
• Ohmic: Closed switch (V
GS
˜ 0).
• On-Resistance:
R
DS(on)
˜
1
2I
DSS
|V
P
|
2
(V
GS
-V
P
)
7. Ampli?er Con?gurations
• Common Source (CS):
A
v
=-g
m
(R
D
?r
d
?R
L
)
R
in
˜8, R
out
˜R
D
• Common Drain (CD, Source Follower):
A
v
˜ 1
R
in
˜8, R
out
˜
1
g
m
?R
S
• Common Gate (CG):
A
v
=g
m
(R
D
?r
d
?R
L
)
R
in
˜
1
g
m
, R
out
˜R
D
8. Power Dissipation
• Power:
P =V
DS
I
D
• Maximum Power: Limited by thermal constraints and safe operating area.
2
Page 3


Formula Sheet for Junction Field-E?ect Transistors
(Analog and Digital Electronics) – GATE
1. Basic Concepts
• JFET Types: N-channel, P-channel.
• Structure: Gate, Drain, Source; channel controlled by gate-source voltage.
• Operation: Voltage-controlleddevice, depletion-modeonly(conductsatV
GS
= 0).
• Operating Regions: Ohmic (Linear), Saturation (Pinch-o?), Cut-o?.
2. JFET Characteristics
• Drain Current (Saturation Region, N-channel):
I
D
=I
DSS
(
1-
V
GS
V
P
)
2
where:
– I
DSS
: Drain current when V
GS
= 0.
– V
P
: Pinch-o? voltage (negative for N-channel).
– V
GS
: Gate-source voltage.
• Ohmic Region:
I
D
=
2I
DSS
|V
P
|
2
[
(V
GS
-V
P
)V
DS
-
V
2
DS
2
]
• Cut-o? Region: V
GS
=V
P
, I
D
= 0.
3. Operating Regions
• Cut-o?: V
GS
=V
P
, I
D
= 0.
• Ohmic (Linear): V
GS
>V
P
, V
DS
<V
GS
-V
P
.
• Saturation (Pinch-o?): V
GS
>V
P
, V
DS
=V
GS
-V
P
.
4. Small-Signal Parameters
• Transconductance:
g
m
=
2I
DSS
|V
P
|
(
1-
V
GS
V
P
)
=
v
2I
DSS
I
D
|V
P
|
• Drain Resistance:
r
d
=
?V
DS
?I
D
˜
1
?I
D
where ?: Channel-length modulation parameter (often small for JFETs).
• Input Resistance: R
in
˜8 (gate-source junction reverse-biased).
1
5. JFET Biasing
• Self-Bias:
V
GS
=-I
D
R
S
I
D
=I
DSS
(
1+
I
D
R
S
V
P
)
2
• Voltage Divider Bias:
V
G
=V
DD
·
R
2
R
1
+R
2
V
GS
=V
G
-I
D
R
S
• Drain-Source Voltage:
V
DS
=V
DD
-I
D
(R
D
+R
S
)
6. JFET as a Switch
• Cut-o?: Open switch (V
GS
=V
P
, I
D
= 0).
• Ohmic: Closed switch (V
GS
˜ 0).
• On-Resistance:
R
DS(on)
˜
1
2I
DSS
|V
P
|
2
(V
GS
-V
P
)
7. Ampli?er Con?gurations
• Common Source (CS):
A
v
=-g
m
(R
D
?r
d
?R
L
)
R
in
˜8, R
out
˜R
D
• Common Drain (CD, Source Follower):
A
v
˜ 1
R
in
˜8, R
out
˜
1
g
m
?R
S
• Common Gate (CG):
A
v
=g
m
(R
D
?r
d
?R
L
)
R
in
˜
1
g
m
, R
out
˜R
D
8. Power Dissipation
• Power:
P =V
DS
I
D
• Maximum Power: Limited by thermal constraints and safe operating area.
2
9. JFET Applications
• Voltage-Controlled Resistor: In ohmic region, R
DS
?
1
V
GS
-V
P
.
• Constant Current Source:
I
D
˜I
DSS
(with V
GS
= 0)
• Uses: Low-noise ampli?ers, analog switches, voltage-controlled attenuators.
10. Design Considerations
• Biasing Stability: Use R
S
for self-bias to stabilize I
D
.
• Pinch-o? Voltage: Ensure V
GS
>V
P
for operation.
• Temperature E?ects: I
DSS
increases, V
P
decreases with temperature.
• Load Line Analysis:
V
DS
=V
DD
-I
D
(R
D
+R
S
)
3