Formula Sheets: Logic Families | Digital Electronics - Electrical Engineering (EE) PDF Download

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Digital Electronics: Logic F amilies F orm ula Sheet for
Electrical GA TE
Common P arameters
• Propagation Dela y :
t
p
=
t
PHL
+t
PLH
2
where t
PHL
is high-to-lo w propagation dela y , t
PLH
is lo w-to-high propagation dela y
(ns ).
• P o w er Dissipation :
P = V
CC
·I
CC
where V
CC
is supply v oltage (V ), I
CC
is a v erage supply curren t (mA ).
• Noise Margin :
NM
H
= V
OH( min)
-V
IH( min)
, NM
L
= V
IL( max)
-V
OL( max)
where V
OH
, V
OL
are output high/lo w v oltages, V
IH
, V
IL
are input high/lo w v oltages.
• F an-Out :
F an-Out=min
(
I
OH( max)
I
IH( max)
,
I
OL( max)
I
IL( max)
)
where I
OH
, I
OL
are output curren ts, I
IH
, I
IL
are input curren ts.
TTL (T ransistor-T ransistor Logic)
• Supply V oltage : V
CC
=5V±10% .
• T ypical V oltage Lev els :
V
OH
=2.4V, V
OL
=0.4V, V
IH
=2V, V
IL
=0.8V
• P o w er Dissipation (Standard TTL) :
P ˜10mW p er gate
• Propagation Dela y (Standard TTL):
t
p
˜10ns
• F an-Out : T ypically 10 for standard TTL.
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Page 2


Digital Electronics: Logic F amilies F orm ula Sheet for
Electrical GA TE
Common P arameters
• Propagation Dela y :
t
p
=
t
PHL
+t
PLH
2
where t
PHL
is high-to-lo w propagation dela y , t
PLH
is lo w-to-high propagation dela y
(ns ).
• P o w er Dissipation :
P = V
CC
·I
CC
where V
CC
is supply v oltage (V ), I
CC
is a v erage supply curren t (mA ).
• Noise Margin :
NM
H
= V
OH( min)
-V
IH( min)
, NM
L
= V
IL( max)
-V
OL( max)
where V
OH
, V
OL
are output high/lo w v oltages, V
IH
, V
IL
are input high/lo w v oltages.
• F an-Out :
F an-Out=min
(
I
OH( max)
I
IH( max)
,
I
OL( max)
I
IL( max)
)
where I
OH
, I
OL
are output curren ts, I
IH
, I
IL
are input curren ts.
TTL (T ransistor-T ransistor Logic)
• Supply V oltage : V
CC
=5V±10% .
• T ypical V oltage Lev els :
V
OH
=2.4V, V
OL
=0.4V, V
IH
=2V, V
IL
=0.8V
• P o w er Dissipation (Standard TTL) :
P ˜10mW p er gate
• Propagation Dela y (Standard TTL):
t
p
˜10ns
• F an-Out : T ypically 10 for standard TTL.
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CMOS (Complemen tary Metal-Oxide-Semiconductor)
• Supply V oltage : V
DD
=3V to 15V .
• T ypical V oltage Lev els :
V
OH
˜ V
DD
, V
OL
˜0V, V
IH
=0.7V
DD
, V
IL
=0.3V
DD
• Static P o w er Dissipation :
P
static
˜1nW to 1 µW p er gate
• Dynamic P o w er Dissipation :
P
dynamic
= C
L
V
2
DD
f
where C
L
is load capacitance (pF ), f is s witc hing frequency (Hz ).
• Propagation Dela y :
t
p
˜10ns to 50ns (dep ends on V
DD
and C
L
)
• F an-Out : T ypically 50 or higher due to lo w input curren t.
ECL (Emitter-Coupled Logic)
• Supply V oltage : V
EE
=-5.2V .
• T ypical V oltage Lev els :
V
OH
˜-0.9V, V
OL
˜-1.7V
• P o w er Dissipation :
P ˜25mW p er gate
• Propagation Dela y :
t
p
˜1ns to 2ns
• F an-Out : T ypically 25 due to high driv e capabilit y .
Comparison and In terfacing
• Figure of Merit :
F OM= P ·t
p
(Lo w er F OM indicates b etter p erformance.)
• TTL to CMOS In terfacing : Use pull-up resistor or lev el shifter if V
CC
?= V
DD
.
• CMOS to TTL In terfacing : Ensure CMOS V
OH
=2.4V , V
OL
=0.4V .
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Page 3


Digital Electronics: Logic F amilies F orm ula Sheet for
Electrical GA TE
Common P arameters
• Propagation Dela y :
t
p
=
t
PHL
+t
PLH
2
where t
PHL
is high-to-lo w propagation dela y , t
PLH
is lo w-to-high propagation dela y
(ns ).
• P o w er Dissipation :
P = V
CC
·I
CC
where V
CC
is supply v oltage (V ), I
CC
is a v erage supply curren t (mA ).
• Noise Margin :
NM
H
= V
OH( min)
-V
IH( min)
, NM
L
= V
IL( max)
-V
OL( max)
where V
OH
, V
OL
are output high/lo w v oltages, V
IH
, V
IL
are input high/lo w v oltages.
• F an-Out :
F an-Out=min
(
I
OH( max)
I
IH( max)
,
I
OL( max)
I
IL( max)
)
where I
OH
, I
OL
are output curren ts, I
IH
, I
IL
are input curren ts.
TTL (T ransistor-T ransistor Logic)
• Supply V oltage : V
CC
=5V±10% .
• T ypical V oltage Lev els :
V
OH
=2.4V, V
OL
=0.4V, V
IH
=2V, V
IL
=0.8V
• P o w er Dissipation (Standard TTL) :
P ˜10mW p er gate
• Propagation Dela y (Standard TTL):
t
p
˜10ns
• F an-Out : T ypically 10 for standard TTL.
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CMOS (Complemen tary Metal-Oxide-Semiconductor)
• Supply V oltage : V
DD
=3V to 15V .
• T ypical V oltage Lev els :
V
OH
˜ V
DD
, V
OL
˜0V, V
IH
=0.7V
DD
, V
IL
=0.3V
DD
• Static P o w er Dissipation :
P
static
˜1nW to 1 µW p er gate
• Dynamic P o w er Dissipation :
P
dynamic
= C
L
V
2
DD
f
where C
L
is load capacitance (pF ), f is s witc hing frequency (Hz ).
• Propagation Dela y :
t
p
˜10ns to 50ns (dep ends on V
DD
and C
L
)
• F an-Out : T ypically 50 or higher due to lo w input curren t.
ECL (Emitter-Coupled Logic)
• Supply V oltage : V
EE
=-5.2V .
• T ypical V oltage Lev els :
V
OH
˜-0.9V, V
OL
˜-1.7V
• P o w er Dissipation :
P ˜25mW p er gate
• Propagation Dela y :
t
p
˜1ns to 2ns
• F an-Out : T ypically 25 due to high driv e capabilit y .
Comparison and In terfacing
• Figure of Merit :
F OM= P ·t
p
(Lo w er F OM indicates b etter p erformance.)
• TTL to CMOS In terfacing : Use pull-up resistor or lev el shifter if V
CC
?= V
DD
.
• CMOS to TTL In terfacing : Ensure CMOS V
OH
=2.4V , V
OL
=0.4V .
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Key Notes
• TTL A dv an tages : High sp eed, robust; Disadv an tages: High p o w er consumption.
• CMOS A dv an tages : Lo w p o w er, high noise margin; Disadv an tages: Slo w er at lo w
V
DD
.
• ECL A dv an tages : F astest switc hing; Disadv an tages: High p o w er, negativ e supply .
• GA TE F o cus : Calculate noise margins, fan-out, and p o w er dissipation; understand
in terfacing issues.
• Units : Use SI units for GA TE (e.g., V , A , W , ns ).
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