Formula Sheets: Sequential Circuits | Digital Electronics - Electrical Engineering (EE) PDF Download

 Page 1


Formula Sheet for Sequential Circuits (Digital
Electronics) – GATE
1. Basic Concepts
• Sequential Circuit: Output depends on present inputs and past states (memory
elements).
• Types: Synchronous (clock-driven) and Asynchronous (event-driven).
• Components: Flip-?ops, latches, counters, registers.
2. Flip-Flops
• SR Flip-Flop:
Q
n+1
=S +R·Q
n
, S ·R = 0
• JK Flip-Flop:
Q
n+1
=J ·Q
n
+K ·Q
n
• D Flip-Flop:
Q
n+1
=D
• T Flip-Flop:
Q
n+1
=T ?Q
n
3. Characteristic Equations
• SR: Q
n+1
=S +R·Q
n
• JK: Q
n+1
=J ·Q
n
+K ·Q
n
• D: Q
n+1
=D
• T: Q
n+1
=T ?Q
n
4. Excitation Tables
SR JK D T
Q
n
Q
n+1
S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0
1
Page 2


Formula Sheet for Sequential Circuits (Digital
Electronics) – GATE
1. Basic Concepts
• Sequential Circuit: Output depends on present inputs and past states (memory
elements).
• Types: Synchronous (clock-driven) and Asynchronous (event-driven).
• Components: Flip-?ops, latches, counters, registers.
2. Flip-Flops
• SR Flip-Flop:
Q
n+1
=S +R·Q
n
, S ·R = 0
• JK Flip-Flop:
Q
n+1
=J ·Q
n
+K ·Q
n
• D Flip-Flop:
Q
n+1
=D
• T Flip-Flop:
Q
n+1
=T ?Q
n
3. Characteristic Equations
• SR: Q
n+1
=S +R·Q
n
• JK: Q
n+1
=J ·Q
n
+K ·Q
n
• D: Q
n+1
=D
• T: Q
n+1
=T ?Q
n
4. Excitation Tables
SR JK D T
Q
n
Q
n+1
S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0
1
5. State Diagram and State Table
• State Equation: Q
n+1
=f(Q
n
,inputs)
• Output Equation: Y =g(Q
n
,inputs)
• Moore Machine: Output depends only on state (Y =g(Q
n
)).
• Mealy Machine: Output depends on state and inputs (Y =g(Q
n
,inputs)).
6. Counters
• Mod-N Counter: Counts from 0 to N -1, requires ?log
2
N? ?ip-?ops.
• Ripple Counter: Asynchronous, each ?ip-?op triggered by previous one.
• Synchronous Counter: All ?ip-?ops triggered by same clock.
• Frequency Division: Output frequency =
Clock frequency
N
.
7. Shift Registers
• Types: SISO, SIPO, PISO, PIPO.
• Shift Operation: Q
n+1
=Q
n
shifted left/right by 1 bit.
• Applications: Data storage, data transfer, serial-to-parallel conversion.
8. Timing Parameters
• Setup Time (t
setup
): Time input must be stable before clock edge.
• Hold Time (t
hold
): Time input must remain stable after clock edge.
• Propagation Delay (t
pd
): Time from clock edge to output change.
• Clock Frequency: f
max
=
1
t
pd
+tsetup
.
9. Finite State Machine (FSM) Design
• Steps:
1. De?ne states and inputs/outputs.
2. Draw state diagram.
3. Create state table.
4. Derive excitation equations.
5. Implement using ?ip-?ops and logic gates.
• State Reduction: Minimize number of states using equivalence.
• State Assignment: Assign binary codes to states.
2
Page 3


Formula Sheet for Sequential Circuits (Digital
Electronics) – GATE
1. Basic Concepts
• Sequential Circuit: Output depends on present inputs and past states (memory
elements).
• Types: Synchronous (clock-driven) and Asynchronous (event-driven).
• Components: Flip-?ops, latches, counters, registers.
2. Flip-Flops
• SR Flip-Flop:
Q
n+1
=S +R·Q
n
, S ·R = 0
• JK Flip-Flop:
Q
n+1
=J ·Q
n
+K ·Q
n
• D Flip-Flop:
Q
n+1
=D
• T Flip-Flop:
Q
n+1
=T ?Q
n
3. Characteristic Equations
• SR: Q
n+1
=S +R·Q
n
• JK: Q
n+1
=J ·Q
n
+K ·Q
n
• D: Q
n+1
=D
• T: Q
n+1
=T ?Q
n
4. Excitation Tables
SR JK D T
Q
n
Q
n+1
S R J K D T
0 0 0 X 0 X 0 0
0 1 1 0 1 X 1 1
1 0 0 1 X 1 0 1
1 1 X 0 X 0 1 0
1
5. State Diagram and State Table
• State Equation: Q
n+1
=f(Q
n
,inputs)
• Output Equation: Y =g(Q
n
,inputs)
• Moore Machine: Output depends only on state (Y =g(Q
n
)).
• Mealy Machine: Output depends on state and inputs (Y =g(Q
n
,inputs)).
6. Counters
• Mod-N Counter: Counts from 0 to N -1, requires ?log
2
N? ?ip-?ops.
• Ripple Counter: Asynchronous, each ?ip-?op triggered by previous one.
• Synchronous Counter: All ?ip-?ops triggered by same clock.
• Frequency Division: Output frequency =
Clock frequency
N
.
7. Shift Registers
• Types: SISO, SIPO, PISO, PIPO.
• Shift Operation: Q
n+1
=Q
n
shifted left/right by 1 bit.
• Applications: Data storage, data transfer, serial-to-parallel conversion.
8. Timing Parameters
• Setup Time (t
setup
): Time input must be stable before clock edge.
• Hold Time (t
hold
): Time input must remain stable after clock edge.
• Propagation Delay (t
pd
): Time from clock edge to output change.
• Clock Frequency: f
max
=
1
t
pd
+tsetup
.
9. Finite State Machine (FSM) Design
• Steps:
1. De?ne states and inputs/outputs.
2. Draw state diagram.
3. Create state table.
4. Derive excitation equations.
5. Implement using ?ip-?ops and logic gates.
• State Reduction: Minimize number of states using equivalence.
• State Assignment: Assign binary codes to states.
2
10. Hazards in Sequential Circuits
• Static Hazard: Unwanted glitch due to multiple paths.
• Dynamic Hazard: Multiple glitches during transition.
• Solution: Redundant terms in K-map or hazard-free design.
3