Formula Sheets: Sequential Circuits | Digital Logic - Computer Science Engineering (CSE) PDF Download

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Sequen tial Circuits F orm ula Sheet
Sequen tial Circuits Basics
• Definition : Digital circuits where outputs dep end on curren t inputs and past states (memory).
• Comp onen ts : Flip-flops, latc hes, registe rs, coun ters, com binational logic.
• State Represen tation : S = {Q
1
,Q
2
,...,Q
n
} , where Q
i
is flip-flop output, 2
n
states for n
flip-flops.
• Clo c k P erio d : T
clk
=
1
f
, where f is clo c k frequency (Hz).
• Propagation Dela y : T
circuit
= T
com b
+T
ff , where T
com b
is com binational dela y , T
ff is flip-flop
dela y (2-5 ns).
• Setup and Hold Time : T
setup
, T
hold
, ensure stable inputs, t ypically 1-2 ns.
Latc hes and Flip-Flops
• Latc h :
– Lev el-sensitiv e, e.g., SR Latc h, D Latc h.
– SR Latc h: Inputs S,R ; Outputs Q,Q ; In v alid state: S =R = 1 .
– D Latc h: Input D , Enable E ; Q
next
=D when E = 1 .
– Dela y: T
latc h
=T
NOR
+T
AND
, t ypically 2-3 ns.
• Flip-Flop :
– Edge-triggered (rising/falling), e.g., SR, D, JK, T Flip-Flops.
– Dela y: T
ff =T
latc h
+T
edge
, t ypically 3-5 ns.
– Clo c k-to-Q Dela y: T
cq
, time from clo c k edge to output, 1-3 ns.
• T yp es and Characteristic Equations :
– SR Flip-Flop: Q
next
=S +RQ , in v alid S =R = 1 .
– D Flip-Flop: Q
next
=D , simplest, no in v alid state.
– JK Flip-Flop: Q
next
=JQ+KQ , toggles when J =K = 1 .
– T Flip-Flop: Q
next
=T ?Q , toggles whe n T = 1 .
• Excitation T able : Maps Q,Q
next
to inputs, e.g., D FF: D = Q
next
, JK FF: J = Q
next
Q ,
K =Q
next
Q .
• Gate Coun t : N
gates
˜ 6-10 p er flip-flop (e.g., D FF: 6 NAND gates).
Race-Around Condition
• Definition : Un w an ted toggling in JK/SR flip-flops when clo c k pulse is high and J = K = 1 (or
S =R = 1 ).
• Condition : Occurs if T
pulse
>T
ff , where T
pulse
is clo c k pulse width.
• Solution : Edge-triggered flip-flops, T
edge
«T
pulse
, or master-sla v e configuration, doubles T
ff .
• Dela y Ov erhead : T
race-free
=T
ff +T
edge
, t ypically 4-6 ns.
• Impact : Increases T
circuit
, a v oided in D/T flip-flops.
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Page 2


Sequen tial Circuits F orm ula Sheet
Sequen tial Circuits Basics
• Definition : Digital circuits where outputs dep end on curren t inputs and past states (memory).
• Comp onen ts : Flip-flops, latc hes, registe rs, coun ters, com binational logic.
• State Represen tation : S = {Q
1
,Q
2
,...,Q
n
} , where Q
i
is flip-flop output, 2
n
states for n
flip-flops.
• Clo c k P erio d : T
clk
=
1
f
, where f is clo c k frequency (Hz).
• Propagation Dela y : T
circuit
= T
com b
+T
ff , where T
com b
is com binational dela y , T
ff is flip-flop
dela y (2-5 ns).
• Setup and Hold Time : T
setup
, T
hold
, ensure stable inputs, t ypically 1-2 ns.
Latc hes and Flip-Flops
• Latc h :
– Lev el-sensitiv e, e.g., SR Latc h, D Latc h.
– SR Latc h: Inputs S,R ; Outputs Q,Q ; In v alid state: S =R = 1 .
– D Latc h: Input D , Enable E ; Q
next
=D when E = 1 .
– Dela y: T
latc h
=T
NOR
+T
AND
, t ypically 2-3 ns.
• Flip-Flop :
– Edge-triggered (rising/falling), e.g., SR, D, JK, T Flip-Flops.
– Dela y: T
ff =T
latc h
+T
edge
, t ypically 3-5 ns.
– Clo c k-to-Q Dela y: T
cq
, time from clo c k edge to output, 1-3 ns.
• T yp es and Characteristic Equations :
– SR Flip-Flop: Q
next
=S +RQ , in v alid S =R = 1 .
– D Flip-Flop: Q
next
=D , simplest, no in v alid state.
– JK Flip-Flop: Q
next
=JQ+KQ , toggles when J =K = 1 .
– T Flip-Flop: Q
next
=T ?Q , toggles whe n T = 1 .
• Excitation T able : Maps Q,Q
next
to inputs, e.g., D FF: D = Q
next
, JK FF: J = Q
next
Q ,
K =Q
next
Q .
• Gate Coun t : N
gates
˜ 6-10 p er flip-flop (e.g., D FF: 6 NAND gates).
Race-Around Condition
• Definition : Un w an ted toggling in JK/SR flip-flops when clo c k pulse is high and J = K = 1 (or
S =R = 1 ).
• Condition : Occurs if T
pulse
>T
ff , where T
pulse
is clo c k pulse width.
• Solution : Edge-triggered flip-flops, T
edge
«T
pulse
, or master-sla v e configuration, doubles T
ff .
• Dela y Ov erhead : T
race-free
=T
ff +T
edge
, t ypically 4-6 ns.
• Impact : Increases T
circuit
, a v oided in D/T flip-flops.
1
Edge-T riggered Latc hes
• Definition : Latc h resp onds only at clo c k edge (rising/falling), prev en ts race-around.
• Op eration : Input sampled at edge, Q
next
stable after T
cq
.
• Timing Constrain ts : T
clk
=T
cq
+T
com b
+T
setup
, ensures correct state transition.
• Dela y : T
edge-triggered
=T
latc h
+T
clk-detect
, t ypically 3-5 ns.
• Gate Ov erhead : N
gates
˜ 8-12 , higher than lev el-sensitiv e latc hes.
Shift Registers
• Definition : Chain of flip-flops for shifting data, e.g., SISO, SIPO, PISO, PIPO.
• Shift Time : T
shift
=n·T
clk
, where n is n um b er of bits.
• Capacit y : S
register
=n·S
bit
, t ypically n = 4,8,16 .
• T yp es :
– Serial-In Serial-Out (SISO): T
load
=n·T
clk
, T
read
=n·T
clk
.
– P arallel-In P arallel-Out (PIPO): T
load
=T
clk
, T
read
=T
clk
.
• Gate Coun t : N
gates
˜n·N
ff , where N
ff ˜ 6-10 p er flip-flop.
• Applications : Data storage, serial-to-parallel con v ersion, dela y lines.
Coun ters
• Definition : Sequen tial circuit to coun t clo c k pulses, e.g., binary , BCD, ring, Johnson.
• Mo dulus : M , n um b er of states, e.g., 4-bit binary: M = 2
4
= 16 .
• State T ransitions : Q
next
=Q+1 mod M , implemen ted with T/JK/D flip-flops.
• T yp es :
– Sync hronous: All flip-flops clo c k ed sim ultaneously , T
coun t
=T
clk
+T
com b
, faster.
– Async hronous (Ripple): Flip-flops clo c k ed sequen tially , T
coun t
=n·T
ff , slo w er.
• Dela y : Sync hronous: T
sync
=T
cq
+T
X OR
, Async hronous: T
async
=n·T
cq
.
• Gate Coun t : N
gates
˜n·(N
ff +2) , where N
ff ˜ 6-10 , plus com binational logic.
• F requency Limit : f
max
=
1
T coun t
, higher for sync hronous coun ters.
Flip-Flop Con v ersion
• Ob jectiv e : Con v ert one flip-flop t yp e to another (e.g., JK to D, T to JK).
• Metho d : Us e excitation table to map inputs, e.g., JK to D: D =JQ+KQ .
• Con v ersion Logic : N
gates
˜ 2-4 p er flip-flop (e.g., AND, OR for JK to D).
• Dela y Ov erhead : T
con v ert
=T
com b
+T
ff , t ypically 5-8 ns.
• Example : T to JK, J =T ·Q , K =T ·Q , T
con v ert
=T
AND
+T
ff .
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Page 3


Sequen tial Circuits F orm ula Sheet
Sequen tial Circuits Basics
• Definition : Digital circuits where outputs dep end on curren t inputs and past states (memory).
• Comp onen ts : Flip-flops, latc hes, registe rs, coun ters, com binational logic.
• State Represen tation : S = {Q
1
,Q
2
,...,Q
n
} , where Q
i
is flip-flop output, 2
n
states for n
flip-flops.
• Clo c k P erio d : T
clk
=
1
f
, where f is clo c k frequency (Hz).
• Propagation Dela y : T
circuit
= T
com b
+T
ff , where T
com b
is com binational dela y , T
ff is flip-flop
dela y (2-5 ns).
• Setup and Hold Time : T
setup
, T
hold
, ensure stable inputs, t ypically 1-2 ns.
Latc hes and Flip-Flops
• Latc h :
– Lev el-sensitiv e, e.g., SR Latc h, D Latc h.
– SR Latc h: Inputs S,R ; Outputs Q,Q ; In v alid state: S =R = 1 .
– D Latc h: Input D , Enable E ; Q
next
=D when E = 1 .
– Dela y: T
latc h
=T
NOR
+T
AND
, t ypically 2-3 ns.
• Flip-Flop :
– Edge-triggered (rising/falling), e.g., SR, D, JK, T Flip-Flops.
– Dela y: T
ff =T
latc h
+T
edge
, t ypically 3-5 ns.
– Clo c k-to-Q Dela y: T
cq
, time from clo c k edge to output, 1-3 ns.
• T yp es and Characteristic Equations :
– SR Flip-Flop: Q
next
=S +RQ , in v alid S =R = 1 .
– D Flip-Flop: Q
next
=D , simplest, no in v alid state.
– JK Flip-Flop: Q
next
=JQ+KQ , toggles when J =K = 1 .
– T Flip-Flop: Q
next
=T ?Q , toggles whe n T = 1 .
• Excitation T able : Maps Q,Q
next
to inputs, e.g., D FF: D = Q
next
, JK FF: J = Q
next
Q ,
K =Q
next
Q .
• Gate Coun t : N
gates
˜ 6-10 p er flip-flop (e.g., D FF: 6 NAND gates).
Race-Around Condition
• Definition : Un w an ted toggling in JK/SR flip-flops when clo c k pulse is high and J = K = 1 (or
S =R = 1 ).
• Condition : Occurs if T
pulse
>T
ff , where T
pulse
is clo c k pulse width.
• Solution : Edge-triggered flip-flops, T
edge
«T
pulse
, or master-sla v e configuration, doubles T
ff .
• Dela y Ov erhead : T
race-free
=T
ff +T
edge
, t ypically 4-6 ns.
• Impact : Increases T
circuit
, a v oided in D/T flip-flops.
1
Edge-T riggered Latc hes
• Definition : Latc h resp onds only at clo c k edge (rising/falling), prev en ts race-around.
• Op eration : Input sampled at edge, Q
next
stable after T
cq
.
• Timing Constrain ts : T
clk
=T
cq
+T
com b
+T
setup
, ensures correct state transition.
• Dela y : T
edge-triggered
=T
latc h
+T
clk-detect
, t ypically 3-5 ns.
• Gate Ov erhead : N
gates
˜ 8-12 , higher than lev el-sensitiv e latc hes.
Shift Registers
• Definition : Chain of flip-flops for shifting data, e.g., SISO, SIPO, PISO, PIPO.
• Shift Time : T
shift
=n·T
clk
, where n is n um b er of bits.
• Capacit y : S
register
=n·S
bit
, t ypically n = 4,8,16 .
• T yp es :
– Serial-In Serial-Out (SISO): T
load
=n·T
clk
, T
read
=n·T
clk
.
– P arallel-In P arallel-Out (PIPO): T
load
=T
clk
, T
read
=T
clk
.
• Gate Coun t : N
gates
˜n·N
ff , where N
ff ˜ 6-10 p er flip-flop.
• Applications : Data storage, serial-to-parallel con v ersion, dela y lines.
Coun ters
• Definition : Sequen tial circuit to coun t clo c k pulses, e.g., binary , BCD, ring, Johnson.
• Mo dulus : M , n um b er of states, e.g., 4-bit binary: M = 2
4
= 16 .
• State T ransitions : Q
next
=Q+1 mod M , implemen ted with T/JK/D flip-flops.
• T yp es :
– Sync hronous: All flip-flops clo c k ed sim ultaneously , T
coun t
=T
clk
+T
com b
, faster.
– Async hronous (Ripple): Flip-flops clo c k ed sequen tially , T
coun t
=n·T
ff , slo w er.
• Dela y : Sync hronous: T
sync
=T
cq
+T
X OR
, Async hronous: T
async
=n·T
cq
.
• Gate Coun t : N
gates
˜n·(N
ff +2) , where N
ff ˜ 6-10 , plus com binational logic.
• F requency Limit : f
max
=
1
T coun t
, higher for sync hronous coun ters.
Flip-Flop Con v ersion
• Ob jectiv e : Con v ert one flip-flop t yp e to another (e.g., JK to D, T to JK).
• Metho d : Us e excitation table to map inputs, e.g., JK to D: D =JQ+KQ .
• Con v ersion Logic : N
gates
˜ 2-4 p er flip-flop (e.g., AND, OR for JK to D).
• Dela y Ov erhead : T
con v ert
=T
com b
+T
ff , t ypically 5-8 ns.
• Example : T to JK, J =T ·Q , K =T ·Q , T
con v ert
=T
AND
+T
ff .
2
P e rformance Metrics
• Clo c k F requency : f
max
=
1
T cq+T
com b
+T setup
, limited b y critical path.
• Propagation Dela y : T
circuit
=T
com b
+T
ff , minimized b y sync hronous design.
• P o w er Consumption : P
circuit
= (N
gates
·P
gate
+N
ff ·P
ff )·f , higher for flip-flops.
• Area : S
circuit
= (N
gates
·S
gate
+N
ff ·S
ff ) , S
ff »S
gate
.
• State Complexit y : C
states
= log
2
M , where M is n um b er of states, impacts N
ff .
• Timing Margin : T
margin
=T
clk
-(T
cq
+T
com b
+T
setup
) , ensures reliable op eration.
Applications and Concepts
• Latc hes/Flip-Flops : Memory e lemen ts, T
ff critical for pip eline registers.
• Shift Registers : Data serialization, buffering, T
shift
k ey for comm unication systems.
• Coun ters : Timers, frequency dividers, f
max
critical for high-sp eed clo c ks.
• Race-Around A v oidance : Edge-triggered flip- flops ensure stabilit y , used in CPUs, FSMs.
• Sequen tial Logic : Finite State Mac hines (FSMs), N
states
= 2
n
, used in con trol units.
• Flip-Flop Con v ersion : Optimizes design, reduces N
gates
in sp ecific applications.
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