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Four Bit Asynchronous Up Counter And Down Counter Electrical Engineering (EE) Notes | EduRev

Electrical Engineering (EE) : Four Bit Asynchronous Up Counter And Down Counter Electrical Engineering (EE) Notes | EduRev

The document Four Bit Asynchronous Up Counter And Down Counter Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Digital Electronics.
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Four Bit Asynchronous Up Counter

Fig. 5.6.1 shows a 4 bit asynchronous up counter built from four positive edge triggered D type flip-flops connected in toggle mode. Clock pulses are fed into the CK input of FF0 whose output, Q0 provides the 20 output for FF1 after one CK pulse.

The rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half the frequency of the CK pulses applied to its input.

The Q outputs then represent a four-bit binary count with Q0 to Q3 representing 20 (1) to 23 (8) respectively.

Assuming that the four Q outputs are initially at 0000, the rising edge of the first CK pulse applied will cause the output Q0 to go to logic 1, and the next CK pulse will make Q0 output return to logic 0, and at the same time Q0 will go from 0 to 1.

As Q0 (and the CK input of FF1 goes high) this will now make Q1 high, indicating a value of 21 (210) on the Q outputs.

The next (third) CK pulse will cause Q0 to go to logic 1 again, so both Q0 and Q1 will now be high, making the 4-bit output 11002 (310 remembering that Q0 is the least significant bit).

The fourth CK pulse will make both Q0 and Q1 return to 0 and as Q1 will go high at this time, this will toggle FF2, making Q2 high and indicating 00102 (410) at the outputs.

Reading the output word from right to left, the Q outputs therefore continue to represent a binary number equalling the number of input pulses received at the CK input of FF0. As this is a four-stage counter the flip-flops will continue to toggle in sequence and the four Q outputs will output a sequence of binary values from 00002 to 11112 (0 to 1510) before the output returns to 00002 and begins to count up again as illustrated by the waveforms in Fig 5.6.2.

Four Bit Asynchronous Down Counter

To convert the up counter in Fig. 5.6.1 to count DOWN instead, is simply a matter of modifying the connections between the flip-flops. By taking both the output lines and the CK pulse for the next flip-flop in sequence from the Q output as shown in Fig. 5.6.3, a positive edge triggered counter will count down from 11112 to 00002.

Although both up and down counters can be built, using the asynchronous method for propagating the clock, they are not widely used as counters as they become unreliable at high clock speeds, or when a large number of flip-flops are connected together to give larger counts, due to the clock ripple effect.

Clock Ripple

The effect of clock ripple in asynchronous counters is illustrated in Fig. 5.6.4, which is a magnified section (pulse 8) of Fig. 5.6.2.

Fig. 5.6.4 shows how the propagation delays created by the gates in each flip-flop (indicated by the blue vertical lines) add, over a number of flip-flops, to form a significant amount of delay between the time at which the output changes at the first flip flop (the least significant bit), and the last flip flop (the most significant bit).

As the Q0 to Q3 outputs each change at different times, a number of different output states occur as any particular clock pulse causes a new value to appear at the outputs.

At CK pulse 8 for example, the outputs Q0 to Q3 should change from 11102 (710) to 00012 (810), however what really happens (reading the vertical columns of 1s and 0s in Fig. 5.6.4) is that the outputs change, over a period of around 400 to 700ns, in the following sequence:

• 11102 = 710
• 01102 = 610
• 00102 = 410
• 00002 = 010
• 00012 = 810

At CK pulses other that pulse 8 of course, different sequences will occur, therefore there will be periods, as a change of value ripples through the chain of flip-flops, when unexpected values appear at the Q outputs for a very short time. However this can cause problems when a particular binary value is to be selected, as in the case of a decade counter, which must count from 00002 to 10012 (910) and then reset to 00002 on a count of 10102 (1010).

These short-lived logic values will also cause a series of very short spikes on the Q outputs, as the propagation delay of a single flip-flop is only about 100 to 150ns. These spikes are called ‘runt spikes’ and although they may not all reach to full logic 1 value every time, as well as possibly causing false counter triggering, they must also be considered as a possible cause of interference to other parts of the circuit.

Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a simple and effective frequency divider, where a high frequency oscillator provides the input and each flip-flop in the chain divides the frequency by two.

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