Four Bit Asynchronous Up Counter And Down Counter | Digital Electronics - Electrical Engineering (EE) PDF Download

Four Bit Asynchronous Up Counter

Fig. 5.6.1 shows a 4 bit asynchronous up counter built from four positive edge triggered D type flip-flops connected in toggle mode. Clock pulses are fed into the CK input of FF0 whose output, Q₀ provides the 2⁰ output for FF1 after one CK pulse.

The rising edge of the Q output of each flip-flop triggers the CK input of the next flip-flop at half the frequency of the CK pulses applied to its input.

The Q outputs then represent a four-bit binary count with Q₀ to Q₃ representing 2⁰ (1) to 2³ (8) respectively.

Assuming that the four Q outputs are initially at 0000, the rising edge of the first CK pulse applied will cause the output Q₀ to go to logic 1, and the next CK pulse will make Q₀ output return to logic 0, and at the same time Q₀ will go from 0 to 1.

As Q₀ (and the CK input of FF1 goes high) this will now make Q₁ high, indicating a value of 2¹ (2₁₀) on the Q outputs.

The next (third) CK pulse will cause Q₀ to go to logic 1 again, so both Q₀ and Q₁ will now be high, making the 4-bit output 1100₂ (3₁₀ remembering that Q₀ is the least significant bit).

The fourth CK pulse will make both Q₀ and Q₁ return to 0 and as Q₁ will go high at this time, this will toggle FF2, making Q₂ high and indicating 0010₂ (4₁₀) at the outputs.

Reading the output word from right to left, the Q outputs therefore continue to represent a binary number equalling the number of input pulses received at the CK input of FF0. As this is a four-stage counter the flip-flops will continue to toggle in sequence and the four Q outputs will output a sequence of binary values from 0000₂ to 1111₂ (0 to 15₁₀) before the output returns to 0000₂ and begins to count up again as illustrated by the waveforms in Fig 5.6.2.

Four Bit Asynchronous Down Counter

To convert the up counter in Fig. 5.6.1 to count DOWN instead, is simply a matter of modifying the connections between the flip-flops. By taking both the output lines and the CK pulse for the next flip-flop in sequence from the Q output as shown in Fig. 5.6.3, a positive edge triggered counter will count down from 1111₂ to 0000₂.

Although both up and down counters can be built, using the asynchronous method for propagating the clock, they are not widely used as counters as they become unreliable at high clock speeds, or when a large number of flip-flops are connected together to give larger counts, due to the clock ripple effect.

Clock Ripple

The effect of clock ripple in asynchronous counters is illustrated in Fig. 5.6.4, which is a magnified section (pulse 8) of Fig. 5.6.2.

Fig. 5.6.4 shows how the propagation delays created by the gates in each flip-flop (indicated by the blue vertical lines) add, over a number of flip-flops, to form a significant amount of delay between the time at which the output changes at the first flip flop (the least significant bit), and the last flip flop (the most significant bit).

As the Q₀ to Q₃ outputs each change at different times, a number of different output states occur as any particular clock pulse causes a new value to appear at the outputs.

At CK pulse 8 for example, the outputs Q₀ to Q₃ should change from 1110₂ (7₁₀) to 0001₂ (8₁₀), however what really happens (reading the vertical columns of 1s and 0s in Fig. 5.6.4) is that the outputs change, over a period of around 400 to 700ns, in the following sequence:

• 1110₂ = 7₁₀
• 0110₂ = 6₁₀
• 0010₂ = 4₁₀
• 0000₂ = 0₁₀
• 0001₂ = 8₁₀

At CK pulses other that pulse 8 of course, different sequences will occur, therefore there will be periods, as a change of value ripples through the chain of flip-flops, when unexpected values appear at the Q outputs for a very short time. However this can cause problems when a particular binary value is to be selected, as in the case of a decade counter, which must count from 0000₂ to 1001₂ (9₁₀) and then reset to 0000₂ on a count of 1010₂ (10₁₀).

These short-lived logic values will also cause a series of very short spikes on the Q outputs, as the propagation delay of a single flip-flop is only about 100 to 150ns. These spikes are called ‘runt spikes’ and although they may not all reach to full logic 1 value every time, as well as possibly causing false counter triggering, they must also be considered as a possible cause of interference to other parts of the circuit.

Although this problem prevents the circuit being used as a reliable counter, it is still valuable as a simple and effective frequency divider, where a high frequency oscillator provides the input and each flip-flop in the chain divides the frequency by two.