Interconnection Structures - Computer Science Engineering (CSE) PDF Download

Interconnection Structures

• The components that form a multiprocessor system are CPUs, IOPs connected to inputoutput devices, and a memory unit.
• The interconnection between the components can have different physical configurations, depending on the number of transfer paths that are available
  • Between the processors and memory in a shared memory system
  • Among the processing elements in a loosely coupled system
• There are several physical forms available for establishing an interconnection network.
  • Time-shared common bus
  • Multiport memory
  • Crossbar switch
  • Multistage switching network
  • Hypercube system Time Shared Common Bus
• A common-bus multiprocessor system consists of a number of processors connected through a common path to a memory unit.
• Disadv.:
  • Only one processor can communicate with the memory or another processor at any given time.
  • As a consequence, the total overall transfer rate within the system is limited by the speed of the single path
• A more economical implementation of a dual bus structure is depicted in Fig. below.
• Part of the local memory may be designed as a cache memory attached to the CPU.

Multiport Memory 

• A multiport memory system employs separate buses between each memory module and each CPU.
• The module must have internal control logic to determine which port will have access to memory at any given time.
• Memory access conflicts are resolved by assigning fixed priorities to each memory port.
• Adv.:
  • The high transfer rate can be achieved because of the multiple paths.
• Disadv.:
  • It requires expensive memory control logic and a large number of cables and connections

Crossbar Switch

• Consists of a number of crosspoints that are placed at intersections between processor buses and memory module paths.
• The small square in each crosspoint is a switch that determines the path from a processor to a memory module.
• Adv.:
  • Supports simultaneous transfers from all memory modules
• Disadv.:
  • The hardware required to implement the switch can become quite large and complex.
• Below fig. shows the functional design of a crossbar switch connected to one memory module.

Multistage Switching Network

• The basic component of a multistage network is a two-input, two-output interchange switch as shown in Fig. below.
  
• Using the 2x2 switch as a building block, it is possible to build a multistage network to control the communication between a number of sources and destinations.
  • To see how this is done, consider the binary tree shown in Fig. below.
  • Certain request patterns cannot be satisfied simultaneously. i.e., if P₁ → 000~011, then P₂ → 100~111 

• Some request patterns cannot be connected simultaneously. i.e., any two sources cannot be connected simultaneously to destination 000 and 001
• In a tightly coupled multiprocessor system, the source is a processor and the destination is a memory module.
• Set up the path → transfer the address into memory à transfer the data
• In a loosely coupled multiprocessor system, both the source and destination are processing elements.

Hypercube System

• The hypercube or binary n-cube multiprocessor structure is a loosely coupled system composed of N=2ⁿ processors interconnected in an n-dimensional binary cube.
  • Each processor forms a node of the cube, in effect it contains not only a CPU but also local memory and I/O interface.
  • Each processor address differs from that of each of its n neighbors by exactly one bit position.
• Fig. below shows the hypercube structure for n=1, 2, and 3.
• Routing messages through an n-cube structure may take from one to n links from a source node to a destination node.
  • A routing procedure can be developed by computing the exclusive-OR of the source node address with the destination node address.
  • he message is then sent along any one of the axes that the resulting binary value will have 1 bits corresponding to the axes on which the two nodes differ.
• A representative of the hypercube architecture is the Intel iPSC computer complex.
  • It consists of 128(n=7) microcomputers, each node consists of a CPU, a floatingpoint processor, local memory, and serial communication interface units.