Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

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Computer Science Engineering (CSE) : Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

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I/O addressing 

  • A microprocessor communicates with other devices using some of its pins. Broadly we can classify them as

– Port-based I/O (parallel I/O) 

  • Processor has one or more N-bit ports 
  • Processor’s software reads and writes a port just like a register 

– Bus-based I/O 

  • Processor has address, data and control ports that form a single bus 
  • Communication protocol is built into the processor 
  • A single instruction carries out the read or write protocol on the bus • Parallel I/O peripheral  

– When processor only supports bus-based I/O but parallel I/O needed 
 – Each port on peripheral connected to a register within peripheral that is read/written by the processor 

Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

Fig. 13.8 Parallel I/O and extended Parallel I/O 

  • Extended parallel I/O
     – When processor supports port-based I/O but more ports needed
     – One or more processor ports interface with parallel I/O peripheral extending total number of ports available for I/O
     – e.g., extending 4 ports to 6 ports in figure 

Types of bus-based I/O:  
Memory-mapped I/O and standard I/O

  • Processor talks to both memory and peripherals using same bus – two ways to talk to peripherals 
     – Memory-mapped I/O 
    • Peripheral registers occupy addresses in same address space as memory 
    • e.g., Bus has 16-bit address
       – lower 32K addresses may correspond to memory 
       – upper 32k addresses may correspond to peripherals 
       –Standard I/O (I/O-mapped I/O)
      • Additional pin (M/IO) on bus indicates whether a memory or peripheral access 
      • e.g., Bus has 16-bit address 
         – all 64K addresses correspond to memory when M/IO set to 0 
         – all 64K addresses correspond to peripherals when M/IO set to 1 

Memory-mapped I/O vs. Standard I/O

  • Memory-mapped I/O
     – Requires no special instructions 
    • Assembly instructions involving memory like MOV and ADD work with peripherals as well 
    • Standard I/O requires special instructions (e.g., IN, OUT) to move data between peripheral registers and memory 
  • Standard I/O 
     – No loss of memory addresses to peripherals 
     – Simpler address decoding logic in peripherals possible 
    • When number of peripherals much smaller than address space then high-order address bits can be ignored
       – smaller and/or faster comparators 

A basic memory protocol 

Interfacing an 8051 to external memory 

8051 has three 8-bit ports through which it can communicate with the outside world. 
 – Ports P0 and P2 support port-based I/O when 8051 internal memory being used 
 – Those ports serve as data/address buses when external memory is being used 
 – 16-bit address and 8-bit data are time multiplexed; low 8-bits of address must therefore be latched with aid of ALE (address latch enable) signal 

Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

Fig. 13.9(a) A basic memory interface 

Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

Fig. 13.9(b) The timing diagram 

The timing of the various signals is shown in Fig. 13.9(b). The lower byte of the address is placed along P0 and the address latch enable signal is enabled. The higher byte of the address is placed along P2. The ALE signal enables the 74373 chip to latch the address as the P0 bus will be used for data. The P0 bus goes into tri-state (high impedance state) and switches internally for data path. The Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev (read) line is enabled. The bar over the read line indicates that it is active when low. The data is received from the memory on the P0 bus. A memory write cycle can be explained similarly. 

Conclusion 

In this lesson you learnt about the basics of Input Output interfacing. In the previous chapter you also studied about some input output concepts. But most of those I/O such as Timer, Watch Dog circuits, PWM generator, Serial and Parallel ports were part of the microcontroller.
 In this lesson the basics of interfacing with external devices have been discussed. The difference between a Bus and a Port should be kept in mind. The ISA bus is discussed to give an idea about the various bus architectures which will discussed in the later part of this course. You must browse various websites as listed below for further knowledge. 

Questions 

1. List at least 4 differences between the I/O devices for a Real Time Embedded System (RTES) and a Desktop PC?

RTES I/OPC I/O 
It has to operate in real time. The timing requirement has to met.requirement has to met. 
 May take little longer and need not satisfy the stringent timing requirement of the user
The I/O devices need not be meant for the human user and may consists of analog interfaces, digital controllers, mixed signal circuits.The I/O for desktop encompasses a broad range. Generally the keypad, monitor, mouse etc which are meant for the human users are termed as I/O. But it could have also the similar I/Os as in case of RTES 
The power consumption of these I/O devices should be limited. There is virtually no strict limit to the power in such I/Os 
The size of the I/O devices should be small to make it coexist with the processor and other devicesGenerally the size is not a problem as it is not meant to be portable


2. Draw the timing diagram of a memory read protocol for slower memory.  What additional handshaking signals are necessary?

Ans: An additional handshaking signal from the memory namely /ready is necessary. The microcontroller inserts wait states as long as the /ready line is not inactive. The ready line in this case is sampled at the rising edge of the third clock phase. Fig.Q2 reveals the timing of such an operation.

Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

Fig. Q2 The Timing Diagram of memory read from a slower 

3. Enlist the handshaking signals in the ISA bus for dealing with slower I/O devices. 

Ans: 

I/O CH RDY  
 I/O Channel Ready allow slower ISA boards to lengthen I/O or memory cycles by inserting wait states. This signals normal state is active high (ready). ISA boards drive the signal inactive low (not ready) to insert wait states. Devices using this signal to insert wait states should drive it low immediately after detecting a valid address decode and an active read or write command. The signal is release high when the device is ready to complete the cycle. 

4. What additional handshaking signals are necessary for bidirectional data transfer over the same set data lines. 

Ans: For an 8-bit data transfer we need at least 4 additional lines for hand shaking. As shown in Fig.Q4 there are two ports shown. Port A acts as the 8-bit bidirectional data bus. Port C carries the handshaking signals.

Write operation: When the data is ready the /OBFA (PC7 output buffer full acknowledge active low) signal is made 0. The device which is connected acknowledges through /ACKA( PC6 acknowledge that it is ready to accept data. It is active low). The data transfer takes place over PA0-PA7. 

Read  operation: When the data is ready the external device makes the /STBA (PC4 Strobe acknowledge active low) line low. The acknowledgement is sent through IBFA (Input Buffer Empty Acknowledge that it is ready to accept data. It is active high). The data transfer takes place.

Interfacing Bus, Protocols, ISA Bus, etc - 2 Notes | EduRev

5.  List the various bus standards used in industry.    

Ans: 

ISA Bus  

The Industry Standard Architecture (ISA) bus is an open, 8-bit (PC and XT) or 16-bit (AT) asymmetrical I/O channel with numerous compatible hardware implementations. 

EISA Bus  

The Extended Industry Standard Architecture (EISA) bus is an open, 32-bit, asymmetrical I/O channel with numerous compatible hardware implementations. The system bus and allows data transfer rates at a bandwidth of up to 33 MB per second, supports a 4 GB address space, 8 DMA channels, and is backward compatible with the Industry Standard Architecture (ISA) bus.  

PCI Bus

The Peripheral Component Interconnect Local Bus (PCI) is an open, high-performance 32-bit or 64-bit synchronous bus with multiplexed address and data lines, and numerous compatible hardware implementations. PCI bus support a PCI frequency of 33 MHz and a transfer rate of 132 MB per second.  

Futurebus+  

Futurebus+ is an open bus, designed by the IEEE 896 committee, whose architecture and interfaces are publicly documented, and that is independent of any underlying architecture. It has broad-base, cross-industry support; very high throughput (the maximum rate for 64-bit bandwidth is 160 MB per second; for the 128-bit bandwidth, 180 MB per second). Futurebus+ supports a 64-bit address space and a set of control and status registers (CSRs) that provides all the necessary ability to enable or disable features; thus supporting multivendor interoperablity.  

SCSI Bus  

The Small Computer Systems Interface (SCSI) bus is an ANSI standard for the interconnection of computers with each other and with disks, floppies, tapes, printers, optical disks, and scanners. The SCSI standard includes all the mechanical, electrical, and
 example, a 4 MB per second device and a 10 MB per second device may share a fast narrow bus. When the 4 MB per second device is using the bus, the transfer rate is 4 MB per second. When the 10 MB per second device is using the bus, the transfer rate is 10 MB per second. However, when faster devices are placed on a slower bus, their transfer rate is reduced to allow for proper operation in that slower environment. 

Note that the speed of the SCSI bus is a function of cable length, with slow, single-ended SCSI buses supporting a maximum cable length of 6 meters, and fast, single-ended SCSI buses supporting a maximum cable length of 3 meters.

TURBOchannel Bus  

The TURBOchannel bus is a synchronous, 32-bit, asymmetrical I/O channel that can be operated at any fixed frequency in the range 12.5 MHz to 25 MHz. It is also an open bus, developed by Digital, whose architecture and interfaces are publicly documented.
 At 12.5 MHz, the peak data rate is 50 MB per second. At 25 MHz, the peak data rate is 100 MB per second.  
 The TURBOchannel is asymmetrical in that the base system processor and system memory are defined separately from the TURBOchannel architecture. The I/O operations do not directly address each other. All data is entered into system memory before being transferred to another I/O option. The design facilitates a concise and compact protocol with very high performance.  

XMI Bus    

The XMI bus is a 64-bit wide parallel bus that can sustain a 100 MB per second bandwidth in a single processor configuration. The bandwidth is exclusive of addressing overhead; the XMI bus can transmit 100 MB per second of data.
 The XMI bus implements a "pended protocol" design so that the bus does not stall between requests and transmissions of data. Several transactions can be in progress at a given time. Bus cycles not used by the requesting device are available to other devices on the bus. Arbitration and data transfers occur simultaneously, with multiplexed data and address lines. These design features are particularly significant when a combination of multiple devices has a wider bandwidth than the bus itself. 

VME Bus 

Digital UNIX includes a generic VME interface layer that provides customers with a consistent interface to VME devices across Alpha AXP workstation and server platforms. Currently, VME adapters are only supported on the TURBOchannel bus. To use the VME interface layer to write VMEbus device drivers, you must have the Digital UNIX TURBOchannel/VME Adapter Driver Version 2.0 software (Software Product Description 48.50.00) and its required processor and/or hardware configurations (Software Support Addendum 48.50.00-A).     

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