Interrupts - 2 | Embedded Systems (Web) - Computer Science Engineering (CSE) PDF Download

The Bus Arbitration 

When there are more than one device need interrupt service then they have to be connected in specific manner. The processor responds to each one of them. This is called Arbitration. The method can be divided into following  

• Priority Arbiter 
• Daisy Chain Arbiter 

Priority Arbiter 

Fig. 15.5 The Priority Arbitration 

Let us assume that the Priority of the devices are Device1 > Device 2 … 

1. The Processor is executing its program.
 2. Peripheral1 needs servicing so asserts Ireq1. Peripheral2 also needs servicing so asserts Ireq2.  
 3. Priority arbiter sees at least one Ireq input asserted, so asserts Int.
 4. Processor stops executing its program and stores its state.
 5. Processor asserts Inta.
 6. Priority arbiter asserts Iack1 to acknowledge Peripheral1.
 7. Peripheral1 puts its interrupt address vector on the system bus
 8. Processor jumps to the address of ISR read from data bus, ISR executes and returns(and completes handshake with arbiter). 

Thus in case of simultaneous interrupts the device with the highest priority will be served. 

Daisy Chain Interrupts 

In this case the peripherals needing interrupt service are connected in a chain as shown in Fig.15.6. The requests are chained and hence any device interrupting shall be transmitted to the CPU in a chain. 

Let us assume that the Priority of the devices are Device1 > Device 2 … 

1. The Processor is executing its program.
 2. Any Peripheral needs servicing asserts Req out. This Req out  goes to the Req in of the subsequent device in the chain
 3. Thus the peripheral nearest to the μC asserts Int.
 4. The processor stops executing its program and stores its state.
 5. Processor asserts Inta the nearest device.
 6. The Inta passes through the chain till it finds a flag which is set by the device which has generated the interrupt.
 7. The interrupting device sends the Interrupt Address Vector to the processor for its interrupt service subroutine.
 8. The processor jumps to the address of ISR read from data bus, ISR executes and returns.
 9. The flag is reset.  

The processor now check for the next device which has interrupted simultaneously. 

Fig. 15.6 The Daisy Chain Arbitration 

In this case The device nearest to the processor has the highest priority 

The service to the subsequent stages is interrupted if the chain is broken at one place. 

Handling a number of Interrupts by Intel 8259 Programmable Interrupt Controller 

The Programmable Interrupt Controller (PlC) functions as an overall manager in an InterruptDriven system. It accepts requests from the peripheral equipment, determines which of the incoming requests is of the highest importance (priority), ascertains whether the incoming request has a higher priority value than the level currently being serviced, and issues an interrupt to the CPU based on this determination. 

Fig. 15.7 Handling a number of interrupts  

Each peripheral device or structure usually has a special program or “routine” that is associated with its specific functional or operational requirements; this is referred to as a “service routine”. The PlC, after issuing an interrupt to the CPU, must somehow input information into the CPU that can point (vector) the Program Counter to the service routine associated with the requesting device.  

The PIC manages eight levels of requests and has built-in features for expandability to other PIC (up to 64 levels). It is programmed by system software as an I/O peripheral. The priority modes can be changed or reconfigured dynamically at any time during main program operation. 

Interrupt Request Register (IRR) and In-Service Register (ISR) 

The interrupts at the IR input lines are handled by two registers in cascade, the Interrupt Request Register (lRR) and the In- Service Register (lSR). The IRR is used to indicate all the interrupt levels which are requesting service, and the ISR is used to store all the interrupt levels which are currently being serviced. 

Priority Resolver 

This logic block determines the priorities of the bits set in the lRR. The highest priority is selected and strobed into the corresponding bit of the lSR during the INTA sequence. 

Interrupt Mask Register (IMR)  

The lMR stores the bits which disable the interrupt lines to be masked. The IMR operates on the output of the IRR. Masking of a higher priority input will not affect the interrupt request lines of lower priority. 

Data Bus Buffer  

This 3-state, bidirectional 8-bit buffer is used to interface the PIC to the System Data Bus. Control words and status information are transferred through the Data Bus Buffer.  

Read/Write Control Logic  

The function of this block is to accept output commands from the CPU. It contains the Initialization Command Word (lCW) registers and Operation Command Word (OCW) registers which store the various control formats for device operation. This function block also allows the status of the PIC to be transferred onto the Data Bus. This function block stores and compares the IDs of all PICs used in the system. The associated three I/O pins (CAS0- 2) are outputs when the 8259 is used as a master and are inputs when the 8259 is used as a slave. As a master, the 8259 sends the ID of the interrupting slave device onto the CAS0 - 2 lines. The slave, thus selected will send its preprogrammed subroutine address onto the Data Bus during the next one or two consecutive INTA pulses.

Fig. 15.8 The 8259 Interrupt Controller 

Fig. 15.9 The Functional Block Diagram 

Table of Signals of the PIC 

Fig.15.10 shows the daisy chain connection of a number of PICs. The extreme right PIC interrupts the processor. In this figure the processor can entertain up to 24 different interrupt requests. The SP/EN signal has been connected to Vcc for the master and grounded for the slaves. 

Fig. 15.10 Nested Connection of Interrupts 

Software Interrupts 

These are initiated by the program by specific instructions. On encountering such instructions the CPU executes an Interrupt service subroutine

Conclusion 

In this chapter you have learnt about the Interrupts and the Programmable Interrupt Controller. Different methods of interrupt services such as Priority arbitration and Daisy Chain arbitration have been discussed.  In real time systems the interrupts are used for specific cases and the time of execution of these Interrupt Service Subroutines are almost fixed. Too many interrupts are not encouraged in real time as it may severely disrupt the services. Please look at problem no.1 in the exercise.  

Most of the embedded processors are equipped with an interrupt structure. Rarely there is a need to use a PIC. Some of the entry level microcontrollers do not have an inbuilt exception handler called trap. The trap is also an interrupt which is used to handle some extreme processor conditions such as divide by 0, overflow etc.  

Question Answers 

Q1. A computer system has three devices whose characteristics are summarized in the following table: 

Service time indicates how long it takes to run the interrupt handler for each device. The maximum time allowed to elapse between an interrupt request and the start of the interrupt handler is indicated by allowable latency.  If a program P takes 100 seconds to execute when interrupts are disabled, how long will P take to run when interrupts are enabled?  

Ans: 

The CPU time taken to service the interrupts must be found out. Let us consider Device 1. It takes 400 μs to execute and occurs at a frequency of 1/(800μs) (1250 times a second). Consider a time quantum of 1 unit. 

The Device 1 shall take (150+50)/800= 1/4 unit
 The Device 2 shall take (50+50)/1000=1/10 unit
 The Device 3 shall take (100+100)/800=1/4 unit 

In one unit of real time the cpu time taken by all these devices is (1/4+1/10+1/4) = 0.6 units 

The cpu idle time 0.4 units which can be used by the Program P. For 100 seconds of CPU time the Real Time required will be 100/0.4= 250 seconds 

Q.2 What is TRAP? 

Ans: 

The term trap denotes a programmer initiated and expected transfer of control to a special handler routine. In many respects, a trap is nothing more than a specialized subroutine call. Many texts refer to traps as software interrupts. Traps are usually unconditional; that is, when you execute an Interrupt instruction, control always transfers to the procedure associated with the trap. Since traps execute via an explicit instruction, it is easy to determine exactly which instructions in a program will invoke a trap handling routine.  

Q.3. Discuss about the Interrupt Acknowledge Machine Cycle. 

Ans: 

For vectored interrupts the processor expects the address from the external device. Once it receives the interrupt it starts an Interrupt acknowledge cycle as shown in the figure. In the figure TN is the last clock state of the previous instruction immediately after which the processor checks the status of the Intr pin which has already become high by the external device. Therefore the processor starts an INTA cycle in which it brings the interrupt vector through the data lines. If the data lines arte 8-bits and the address required is 16 bits there will be two I/O read. If the interrupt vector is a number which will be vectored to a look up table then only 8-bits are required and hence one I/O read will be there.