MOS Transistors - I - VLSI Circuits & Systems Video Lecture - Computer Science Engineering (CSE)

hello and welcome to today's lecture on
MOS transistors this is the first
lectures on this topic as I mentioned in
the last lecture our course will be
based on CMOS circuits because CMOS is
the technology of choice today and we
shall start we shall follow a bottom-up
approach in the bottom-up approach as
you know we start with very simple
things and we shall start with MOS
transistors and then we shall gradually
discuss MOS inverters most complicated
circuits and other things and so today
is the first lecture on MOS transistors
and here is legend of today's lecture
after giving a brief introduction I
shall discuss structure of MOS
transistors you will see there are
different types of MOS transistors
available and I shall discuss all of
them one after the other and then I
shall discuss fabrication steps of CMOS
transistors because this understanding
of this fabrication step is necessary to
know about how actually CMOS circuit
circuits are realized and then what are
the complicated complicacy I mean
complications and steps involved in it
ok as you know the base semiconductor
material used for the fabrication of MOS
integrated circuits is silicon silicon
is the materials material which is
available in abundance in nature and it
is very cheap so there is no dearth of
raw material in the nature you get
plentiful of I mean silicon in the form
of silicon dioxide or sand however you
have to use a very purified form of
silicon for the fabrication of VLSI
circuits so usually by reacting silicon
dioxide or sand with carbon the the
silicon is purified to a great extent
then it is used for the purpose of
fabrication of
VLSI circuits and here we shall be using
the term moss what do you really mean by
moss a most ends for
metal-oxide-semiconductor
you will see these transistors are
realized by using three different types
of material one is metal metal is
usually aluminum or sometime polysilicon
is also used for the purpose of
conductions conducting material and
oxide is your silicon dioxide which is
which is used as an insulating layer and
semiconductor is silicon with impurity
as you know silicon in the pure form is
not a conductor is an insulator however
you have to add some impurity to realize
I mean to make it semiconductor that
means it will be partially conducting
and then you will be creating pattern
layers of three conducting materials the
conducting materials are metal in the
form of aluminum and then polysilicon
which is also a conducting material
which is used for making
interconnections among different parts
of the circuit then diffusion diffusion
is also a conducting layer which will be
created by two usually two processes
another one process is known as
diffusion another is ion implantation
then these three layers are actually I
mean realized one after the other using
silicon dioxide as an in as an
interfering layer in the four in the
form of a sandwich
so the sandwich like structure of is
realized to implement MOS transistors
and we shall see the fabrication of MOS
transistors involve a series of photo
lithographic techniques and chemical
processes involving oxidation of silicon
to implement to realize silicon dioxide
diffusion of impurities into the silicon
to to
and n plus or P plus regions and
deposition and etching of aluminum that
means which are you which is used for
the purpose of interconnecting different
earlier so itching of aluminum
polysilicon on poly on silicon to
provide interconnection so with this
brief introduction let us have a look at
the structure of a MOS transistor so as
you can see this simplified diagram of a
MOS structure which is shown here it has
got two two regions this is the
substrate the substrate is either
lightly doped p-type or n-type here I
have not shown any any anything but it
can be either PTA lightly doped p-type
or lightly doped n-type and then you
have got you will be creating the on the
I mean two highly doped regions islands
you can say which are known as source
and drain so on a lightly doped
structure substrate of silicon two
islands of diffusion regions called
source and drain and this source and
drain which are heavily doped are of
opposite polarity of that of the
substrate so that means if the substrate
is lightly doped p-type then these
diffusion regions that means force and
drain will be of n type n plus type and
these are known as source and drain as
you can see here and of course for
taking interconnection you can see metal
layer has been deposited for
interconnecting to other parts of the
circuit then between these two islands
source and drain a thin insulating layer
of silicon dioxide is formed you can see
this is the thin layer of silicon
dioxide which is also known as thin ox
thin layer of silicon dioxide and on and
on top of this a conducting material
made of poly silicon this is the poly
silicon layer which has been deposited
on this thin layer of silicon dioxide
and then on top of the fall silicon you
can deposit metal for making
interconnections and this forms the gate
that means on top of the polysilicon the
metal layer is deposited and this forms
the gate now this is the structure
generalized structure of a MOS
transistors and as I told you have two
alternatives you can have either a
p-type substrate or n-type substrate so
whenever you are using p-type substrate
and these these heavily doped regions
are n-type called n plus and n plus then
we realize a n MOS transistor now the
most transistor operation is based on
the flow of current in this channel
region which is under this silicon
dioxide layer this is the channel region
this flow of current between source and
drain in this channel region now you see
in this form in this original form
there cannot be any flow of current
because flow of current requires some
carrier so in absence of any carry
carrier there cannot be any flow of
current so you have to create some camp
carrier charge carrier so that current
can flow in this channel region and for
that purpose there are two two different
techniques are used one is known as
enhancement mode in this mode what is
being done a positive voltage is applied
on the gate and whenever a positive
voltage is applied applied on the gate
it will induce a charge of opposite
polarity on the other side of the
silicon dioxide so in this region in
this channel region charge of opposite
polarity will be induced or in other
words an inversion layer is created so
that inversion layer is made of
electrons in this particular case and
then electrons forms the channel I mean
a channel in in this region that
electrons we is it can be used to carry
current between source and drain since
in this particular case you are applying
a voltage to create the channel that
means you are creating an inversion
layer and by controlling the gate
voltage the flow of current between the
source on source and drain is carried
out and that is the reason why it is
called n MOS enhancement type transistor
so in this particular case originally
there is no charge carrier but you are
applying a positive voltage of
sufficiently I mean sufficiently high
positive voltage to create a charge of
opposite polarity in this particular
case electron for the for for the flow
of current between source and drain now
is it the only way of creating the
conducting path another alternative is
there in which case why you can create
the channel region you can actually in
you can implement by using an
implantation you can you can create
electrons you can put electrons in this
region that means in the absence of any
go gate voltage a channel is formed and
electrons are available in this region
and as a consequence even when the gate
voltage is zero current can flow between
source and drain and you may say that in
this particular case how do you really
stop the flow current what you can do
you can apply a negative voltage to the
gate and obviously if you keep on
increasing the negative voltage on the
gate then it will gradually deplete this
region that means we please the region
from the charge carriers that means the
electrons which have been deposited here
will be removed whenever a negative
voltage is applied and that will induce
holes and holes will actually remove
these electrons so here also
that means by applying a negative
voltage starting from zero to some
negative voltage you can control the
flow of current between the source and
drain so thus you have realized a n Mo's
depletion type transistor so basic
structure remaining same except you are
here at the time of fabrication you are
creating the channel region by diffusion
process then let us come to the third
alternative where you are starting with
starting with a n-type substrate that
means this is a lightly doped substrate
and then in this case these heavily
doped regions will be of p-type that
means here it will be P plus and P plus
which will form the source and drain
here also you have got two types P Mo's
enhancement type so in this K in the in
this case there is no I mean flow of
current when the gate voltage is zero
but if you apply a negative voltage
voltage with respect to the source and
if the gate voltage is sufficiently high
it will induce holes in this region and
that will that the hole will holes will
act a charge carrier I mean current
carrier between the source and drain and
current can flow between the source and
drain and this is how the P Mo's
enhancement type transistor is realized
and I have not shown the symbols here
you can see this is the symbol of a n
MOS enhancement type transistors there
are different several types I mean
different types of symbols used in the
literature but it is the most commonly
used symbol of N Mo's enhancement type
transistor similarly this is the most
commonly used symbol of n Mo's depletion
type transistor and then this is the
most commonly used symbol of P Mo's
enhancement type transistor then the
fourth type of n MOS transistor that is
your P Mo's depletion type in this case
just like the n MOS Dupree
type the holes are implanted in this
region to create to to have channel even
when the gate voltage is zero and then
you can apply a positive voltage to the
gate to gradually reduce the number of
charge carriers in this channel region
and you can this in this way you can
control the flow of current so you can
have P Mo's depletion type transistor so
you can see you can have four different
types of transistor in most using MOS
technology in MOS enhancement type in
most depletion type P Mo's enhancement
type and P Mo's depletion type now one
at this point I should tell you about
another important point you can see in
this particular case the current flow
take place by controlling only one form
of charge carrier that means either you
are controlling the electrons electron
is taking part in the flow of current or
holes are taking part in the flow of
current that means in case of n MOS
transistors the electrons are taking
part in the flow of current on the other
hand in P Mo's transistors the holes are
taking part in the flow of current and
that is the reason why most devices are
known as unipolar devices in contrast to
bipolar devices
you know those bipolar devices the those
are realized by using say Junction
transistors for example those are
bipolar devices because the current flow
take place by the by mean current flow
can take place and where both electrons
and holes take part that means current
flow occurs because of electron hole
recombination that does not occur in
case of MOS devices and that is the
reason why most devices are known as
unipolar devices okay okay so now let us
switch gear and let us have discussion
on fabrication steps of CMOS transistors
so we have seen
different types of MOS transistors
structures how do you really fabricate
them this is very interesting and
obviously we cannot really devote much
time on it but remaining part of this
lecture I shall devote to fabrication
steps of CMOS transistors so as I have
mentioned the first step is the is is is
the realization or creation of a wafer
so wafer is the is the material which is
also called substrate on which the the
VLSI circuits are fabricated how's it
realised so what is being done the
purified silicon is held in molten state
at about 1500 degree centigrade as you
can see in this cubicle the crucible in
this crucible the the silicon is kept in
molten form and it is it is in very
highly purified form how the
purification is done that I have not
discussed but I have already mentioned
that by reacting with carbon you can
create the yet highly purified form of
silicon so which is kept in a molten
form so this is the metal Sulli melted
silicon at 1500 degree centigrade and
now what you do a seed crystal is slowly
withdrawn after bringing bring in
contact with the molten silicon so here
here is a seed crystal which is slightly
dipped in this molten silicon then it is
gradually withdrawn very slowly as it is
gradually withdrawn the the the the
molten silicon comes in contact with
that and it gets it gets attached to
this seed and takes the takes the
crystalline form and as a result as you
gradually withdraw it from the molten
silicon and ignored in this form is
created in addition to this whenever you
do the
withdrawal that time you usually insert
some dopant gas inside this chamber what
is the purpose of this dopant dopant gas
as I mentioned whenever you do the
fabrication the wafer has to be either
slightly doped lightly doped p-type or
n-type how do you really get this
lightly doped p-type or lightly doped
n-type this is done at this step that
means dopant of suitable type is in is
is passed through this chamber as you
can see it is introduced here and is
coming out from here so it is introduced
in this chamber and as a consequence the
the egg not in got that you get is
essentially lightly doped p-type or
n-type it can be either way it can be
done in any one of the two ways then
after the withdrawal of the seed and in
got of several centimeters long three to
four centimeters long and eight to ten
centimeter in diameter is captained then
these this in got is sliced you can see
this is sliced so this is this forms the
wafer so this this slice this slide
after slicing this in got we get a
number of wafers and the wafer is the
base material that is being used for the
purpose of fabrication then you have to
follow a number of steps for the purpose
of fabrication of MOS transistor so you
start with blank wafer build inverter
form from the bottom up so we shall show
how the inverter can be realized but you
can create more complicated circuit but
here I shall show the formation of an
inverter simple inverter so first step
will be to form a n well so you know the
most common type is n well so you have
started with a p-type substrate and as
you know on a p-type substrate you can
realize n MOS transistors depletion type
or n n n span
type but CMOS will require both n MOS
and CMOS as I have told you can have
four different types of transistors than
CMOS which stands for complementary Mo's
requires two types of transistors one
p-type transistor another is n-type
transistor for example a simple inverter
will require a p-type here it is from
the symbol it is very clear that it is a
p-type enhancement type transistor you
will also require a n-type n MOS
transistor so these two together will
form an inverter so here you will apply
VDD here will apply ground and then you
will take you will apply the input here
we will take the output from here so you
can see a complementary Mo's circuitry
requires two types of tenses to come to
complementary types of transistor 1 is P
MOS which acts as pull of network and
the n MOS transistor will act as
pulldown network so here it is a very
simplified form of circuit that is your
inverter you can create very complex
circuit in that case the generalized
structure will be like this you will
have a P MOS network and will have
another network n MOS network and you
will apply inputs to both P Mo's and n
MOS network and it will take the output
from here so here is the various inputs
and here is your output and of course
this p MOS network is connected to VDD
ground and sorry n Mo's network is
connected to ground
and PMO's Network is going to take to
supply voltage VDD so this is the
complementary CMOS so we shall see the
fabrication of this inverter how it is
being done so first thing to be done is
to form an n-well why do you require an
N well because you will require a P MOS
transistor as well for the realization
of a CMOS circuit and these are the
steps cover wafer with protective layer
of silicon dioxide then remove layer
where n wells should be built so this
will require two steps cover wafer with
protective layer of silicon dioxide how
it can be done that can be done by a
process known as oxidation oxidation can
be done by hitting this wafer the
substrate in a in a in a chamber like
this one
hitting chamber like this this one and
then bypassing either oxygen or or or
water vapor so whenever you are passing
oxygen then it is called dry oxidation
then thin form of silicon dioxide is
created on the other hand whenever will
be passing I mean
causing the water vapor then thick form
of silicon dioxide will be deposited but
its quality will not be very good it
will be little porous type and it is
called thick oxide silicon dioxide so
you can use either oxygen or water
vapour for the purpose of end up in the
oxidation process and to realize the
silicon dioxide layer on top of this
substrate then remove the layer where n
wells should be built this removal of n
well from the I mean removal of silicon
dioxide where n well should be formed
requires a photo lithographic process
and then it will implement or defuse end
dopants into exposed wafer and then you
will strip of silicon dioxide so you can
see you are starting with substrate then
you are growing silicon dioxide on top
of the silicon wafer how it is being
done 900 to 1200 degree centigrade it is
heated and with either water vapor or
oxygen in the oxidation furnace as I
have already told and after that you do
the photo lithographic process that
means you deposit photographer tog I
mean email photographic emulsion
photoresist on top of the silicon
dioxide and then it is spread uniformly
by spinning it at little high speed then
you expose it to light with the help of
a mask so you require a mask and this
portion is not exposed as you can see
and then after this this portion is not
exposed so this photoresist can be
easily removed from here and after that
by a process known as itching the
silicon dioxide will be removed H oxide
with hydrofluoric acid so the by
reacting with this hydrofluoric acid
this silicon dioxide is removed so you
have now exposed substrate here and
actually this etching process you are
using an chemical such that it reacts
only with the silicon dioxide not with
the silicon so only at X oxide when
resist has been exposed so this portion
is silicon dioxide is removed but not
the top top portion then of course you
will remove the strip of the remaining
photoresist use mixture of acids called
piranha h so this is the this is another
etching process where you have removed
this further this photoresist from the
top of the silicon dioxide layer the
necessary to resist okay so it is
necessary to so resist does not melt in
the next step then what will you do you
will form the n-well is formed with
diffusion or ion implantation as I told
there are two types of two ways of
realizing diffusion region one is you
can again put that wafer in a chamber
and you can pass suitable dopant through
that chamber and it is heated at a very
high temperature and after some time you
have to give suitable time I mean devout
time of suitable duration such that the
dopants can penetrate up to certain
layer and after that you have to do what
is known as drive-in process you have to
simply heat it up for certain duration
so that the dopants can get stabilized
and gets uniformly distributed within
that certain region so these are the two
stage plus wafer in furnace with arsenic
gasps this is the dopant used for the
for dispersal for the creation of n well
and heat until arsenic atoms diffuse
into X plus silicon this is the drive-in
process another alternative as I told is
ion implantation either of the two can
be used blast wafer with beam of arsenic
ions ions blocked by silicon dioxide
only enter exposed area that means here
you know this this silicon dioxide is
now acting as a kind of protecting layer
so only this part will be we have the
diffusion and this the other part will
not have the diffusion that means the
arsenic ions will be we will be able to
pass through this exposed area but not
through the silicon dioxide layer okay
so this is how the n-well is formed so
you have got lightly doped area of
p-type and lightly doped area of n-type
so where you can create two different
types of transistors
so now you have the substrate with
n-well so strip of the remaining oxide
using hydrofluoric acid then back to
Bayer wafer with n well so this is what
is being shown in this diagram
so subsequent steps involves similar
series of steps to define areas where
transistors are we formed so formation
of n well by an implantation followed by
driving step as I have already told this
step I have already discussed this is
done by using mask 1 so this is the mask
1 this is the mask 1 and coming to the
second step which requires formation of
poly silicon layer so deposit very thin
layer of gate oxide so first step is
very thin layer of silicon dioxide is
deposited again by the that dry
oxidation process as I told it will be
heated in a furnace and oxygen will pass
through the chamber and silica very thin
silicon dioxide layer will be formed so
this is what is being done to create the
thin oxide layer and then on top of that
you will deposit polysilicon layer and
poly scale polysilicon layer is
deposited by using a technique known as
chemical vapour deposition or CVD on the
on top of this silicon dioxide layer so
for this purpose what you have to do you
have to place wafer in a furnace with
silane gas from firms many small
crystals like called colic poly crystal
poly silicon poly crystalline layers and
heavily doped 2 to be good conductors
since this is heavily doped so it will
form a good conductor because this will
be used for the purpose of
interconnection so this polysilicon must
be a good conductor relatively good
conductor because it will be used as a
interconnection layer to connect
different parts of the circuit ok so
this is what this is another mask is
used for the purpose of
creating that pattern polysilicon layer
so use the same photo lithographic
process to pattern polysilicon so
earlier for the polysilicon was
deposited on the entire surface now you
have to create a pattern layer with the
help of this mask called mass 3 so
formation of pattern polysilicon regions
and you can see only polysilicon is
present in these layers and for from
other parts of the substrate poly
silicon has been reformed that means
only where transistors are to be formed
there the poly silicon is deposited so
it is removed from the remaining portion
so you can see here essentially that
gate has been formed gate portion so
this is the gate of the n MOS transistor
this is the gate of the p MOS transistor
so here you have got thin oxide layer
and the poly silicon layer here also
thin oxide layer and policy will follow
silicon layer only difference is here
you have got the lightly doped p-type
substrate and here you have got lightly
doped n-type region within the N well
okay now what you have to do you have to
create diffusion you have to create
those you know source and drain regions
so you have to use oxide and and masking
to expose where n plus dopants should be
diffused or implanted so either you will
use diffusion process or ion
implantation to realize those source and
drain regions so n diffusion from n MOS
source drain and n well contact and
formation of n diffusion is done with
the help of an N plus mask which is in
effect ended with a mask for so you have
got another mask called mask for to
realize to define those you know that
those source and drains of the n MOS
transistors
so pattern oxide with four main class
region so this is the mask of the N
diffusion and this help and I in process
where get block the diffusion so here
you can see this portion there will be
no diffusion and the polysilicon and
thin silicon dioxide will protect the
this the channel region where channel
region will form and only these two
areas will be we have the source and
drain regions ability of regions when
you carry out those diffusion or ion
implantation so now you have done that n
plus diffusion so as I told historically
dopants were diffused by the diffusion
process but nowadays ion implantation is
the technique which is commonly used
because of its high accuracy you know
diffusion whenever you do the diffusion
then the these regions are not very
accurately defined on the other hand by
using because this this lines will not
be straight lines so it will be somewhat
like this somewhat like this but
whenever you do by using ion
implantation then you can different then
create those n plus regions very nicely
so you can see 3 n plus regions have
been created source and drain
another is n well contact here n plus
region you have to actually connect this
n well to V DT and for that purpose and
n plus region is created here so these 3
are created by this n plus diffusion
then you have to strip of oxide to
complete patterning process oxeye oxide
is removed which was acting as a
protecting layer for the other parts of
the substrate then you have to do P plus
diffusion so for the purpose of P plus
diffusion you will require another mask
so that is your step 5 so you have to
follow the similar steps to form P plus
diffusion region only difference is you
have
use a different kind of dopant dopant
type will be different and formation of
n diffusion is done using p+ mask which
is usually a negative form of n plus
mask because as you know where where you
will create n MOS transistor there you
will not create P plus transistor so
just the opposite that is the reason why
these two are of opposite type a
negative of n n plus mask so essentially
to save the cost of TA making the mask
so this is this is how the P plus
diffusion is done as you can see here P
plus diffusion is done in three regions
first the source and drain region of the
P Mo's transistor and also another P
plus region is created here to make
contact with the P substrate because you
will see later on that this substrate
has to be connected to ground then the
substrate has to be connected to ground
and to make contact with that substrate
this P plus region is created so you can
see three P plus regions have now
created and so you have got a n MOS
transistor a P MOS transistors in
addition to two contacts one for
connecting the substrate to ground
another for connecting the N well to
power supply or VDD now you will you
have to make a circuit so so far here
you have got two transistors you have to
interconnect them to form an inverter or
some you have to in the inverter may be
part of a more complicated circuit so
you can see here you have to now make
contacts so another mask is required so
thick silicon dioxide is grown all over
and then contact card definition using
another mask mask six so he will require
a separate mask to create contacts
contacts I mean wherever you have to
make contact with other parts of the
circuit and mask is created accordingly
so now you need to wear together the
device that means all these devices are
to be wet
together using this and for that purpose
you require these contacts scoff chief
with thick field oxide so this thick
field oxide is created by usually by
weight oxidation as I have discussed
earlier then etch oxide wear contacts
turn and cuts are needed again by using
that photo photo lithographic process
you will make those you will remove
those thick oxide layers from these
regions where context has to be
established and then for making the
contact you have to do I mean you have
to use a metal layer so for that purpose
entire entire chip entire substrate will
be covered with metal usually aluminum
so the whole chip then has metal
deposited over its surface to its
thickness of 1 micron the metal layer is
then patterned by photolithography
process to form interconnection pattern
using mask 7 so you will require another
mask 2 to define the interconnection
pattern so you may have to connect that
inverted to another part of the circuit
so input has to come from one part
output has to go to another part of the
circuit so that is being defined with
the help of this mask 7 so you can see
this is the mask 7 for creating the
pattern metal layer another step is also
necessary which is known as over
glassing so over glassing is done by
overall passivation layer and then this
mask is required to define the openings
for access to bonding pads
so once the chip is created you know you
have to take interconnect connections to
the outside world then you have to form
a package so for that purpose you have
to again make holes at the appropriate
places not only for taking
interconnection but also for the purpose
of testing so to test different parts of
the circuit you have to
you have to make contacts at different
points within the chip so that is done
in this step this over glassing step so
were classing is done by overall
passivation layer and this mask is
required to define the openings to
access for access to bonding pads so
they will be connected to the bonding
back pads and then you will form a
package by that well inline package of
some other kind of package and then it
will be available in the market before I
conclude this part I think I should tell
about another alternative way of
realizing CMOS circuits and that
approach is known as silicon on
insulator so here we have seen that in
the the conventional approach which is
also known as bulk CMOS so here what you
are doing you are starting with a
substrate and then you are creating the
n-well you are creating the transition
Mo's and P Mo's land mass and P Mo's
transistors here is the n MOS transistor
here you are creating the P Mo's
transistors this is the channel region
then you are doing the interconnection
you are taking a R and you can see this
is the you can say this is the bulk you
know substrate and in this case this
substrate is entire substrate is
connected with this is the P plus region
is created and this is connected to
ground and similarly the entire entire
you know that this is the well is
connected to VDD this is the box image
here this is one approach another
approach is you will start with the
substrate
then you will deposit silicon dioxide
layer so here is your sio2 so this is
the insulator and on top of this you
will create those various transistors
that means you will form a n MOS
transistor you will form a P MOS
transistor then you will do the
interconnections and so on so you can
see this is called silicon on insulator
this is an insulator and on top of this
insulator you are creating different
transistors and then of course you will
be doing interconnections among them so
you can create n-type transistor you can
create p-type transistor here you are
not forming any well but on a on a on a
silicon dioxide layer you are forming
different types of transistors and
interconnecting them and this is known
as silicon on insulator or SOI so there
is clearly there are two two different
groups for example Intel Texas
Instruments they are following this
approach bulk CMOS approach for
realizing VLSI circuits on the other
hand the SOI approach is being followed
by IBM IBM is using sy approach for
realizing VLSI circuits and it has been
found that this SOI approach has some
good features bulk CMOS also have some
good features so that means these two
have approaches have their own
advantages and disadvantages
particularly SOI approach has been found
to be very suitable for low voltage and
at low voltage it gu gives you very good
quality transistors but it has other
problems but that
means all I am trying to tell that this
bulk CMOS and sy these two are two
alternative approaches available for the
realization of CMOS VLSI circuits and
some fab houses are realizing VLSI
circuits using box CMOS and some fab
houses like IBM they are realizing VLSI
circuits by following SOI approach okay
coming to the last slide you have to
make a kind of layout I have I have
simply shown the formation of an in in
in so inverter so and I have shown you
will require a number of masks to
realize the to create that create
different transistors and make them in
make the interconnections so chips are
specified with set of masks we have seen
eight mass eight steps are required and
eight masks a liquid and minimum
dimension of masks determine transistor
size so they are you know the masks will
be created where you have to those are
nothing but you know you have to create
the kind of pattern Geographic patterns
and they will have some separation some
you have to maintain some width like
that and that will decide the speed cost
and power and if a parameter known as
feature size F is used which is
essentially a distance between source
and drain and it is said by the accuracy
of the photo lithographic technique
available on that date and with the
improvement of this photographic
technique photo lithographic technique
these dimensions are getting reduced
gradually as you know earlier you had
500 micron now you are close to 33
micron and this is happening because of
the advancement of photo lithographic
and other technique
so this minimum width decides the
feature size and feature size improves
30% every three years or so you may have
you may have heard of Moore's law
so Moore's law tells that every 18
months the number of transistors on a
wafer will double how it is happening
the feature size is decreasing and
normalized for feature size when
describing design goals and whenever you
are making the making the pattern that
means the layout then you have to follow
some design rules these designs rules
are specified in terms of a parameter
known as lambda and all these rules are
expressed in terms of lambda lambda is
nothing but this feature size by two
that means whenever it is a point six
micron process then lambda is equal to
0.3 micron okay so that means the layout
is created by following a number of
design rules those designs rules are
specified in terms of lambda that means
the maximum channel length should be 2
lambda
I mean minimum channel length should be
2 lambda like that which should be say
lambda and those I am NOT going into the
details of those design rules but they
are specified in terms of lambda okay so
this is how you will be creating layout
and you will realize a complex VLSI
circuit okay
so with this we have discussed to
summarize what we have discussed today
we have discussed the you know the
structure of MOS transistors and we have
seen there are four different types of
transistors possible in MOS N Mo's
enhancement type n Mo's depletion type P
Mo's enhancement
I and PMO's NMOS enhancement type and P
Mo's depletion type and you can use them
to realize circuits different types of
functional circuits like inverter NAND
gate nor gate and other things and then
we have discussed the fabrication steps
particularly fabrication steps of a CMOS
circuit and we have seen there are two
basic approaches that is one is your one
is based on the traditional approach
bulk CMOS another is your silicon on
insulator approach now I would like to
give you some references so this first
book by can and kin CMOS digital
integrated circuit this book gives you
the background material that will be
required for this course it discusses in
details of CMOS circuits starting with
MOS transistor MOS inverter most
complicated circuits similarly waste and
elegance books also gives you necessary
background for CMOS CMOS circuits then
coming to our low power circuits this
book is very good by --velum --velum or
and el-masri
low power VLSI CMOS circuits but
unfortunately as you can see this book
was written in 1995 it is little old and
another book is also there by anon
speech and ocassion and Robert W border
son low power digital CMOS circuit
design published by kloewer academic
that also published in 1995 so these two
books are primarily on low power CMOS
circuit design but unfortunately these
are not available in Indian Edition so I
requested the library to purchase few
copies of these books these books may be
available in the library
another recent book is a edited version
edited by Kristian pig-out and loop our
CMOS circuits technology logic design
and CAD tools and this is a more recent
book however you will see that major
part of my lectures particularly in the
later part will be based on material
taken from papers I cannot really give
you any I mean copies of everything but
later on I shall provide you some of
these papers copies of some of these
papers and lecture notes are also
available but it may not be necessary
for you because these lectures will be
uploaded in the in the in our CT website
so you can access them maybe after one
or two days and you can go through them
again and again if necessary so with
this we have come to the end of today's
lecture in the next lecture we shall
discuss about a model by which you can
explain the operation of PMO's
transistors and that is known as fluid
model that we shall discuss in the next
class thank you very much
you