Open Collector Gates Electrical Engineering (EE) Notes | EduRev

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Electrical Engineering (EE) : Open Collector Gates Electrical Engineering (EE) Notes | EduRev

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Open Collector Gates

Fig. 3.4.1 shows the internal circuit of an open collector NAND gate. The grey area illustrates a single gate within an IC. Instead of the normal Totem Pole output stage, the single output transistor T3 has its collector brought out to an external pin, which can be connected to an external power supply, at a different voltage to the VCC supply of the IC, via an external load resistor REXT.

In Fig. 3.4.1, when both inputs A and B are at logic 0, the high voltage applied to T1 base will cause it to turn on, so that T1 collector will go to near 0V and T2 will turn off.

As T2 is off there will be virtually no current through R3 so the voltage at T3 gate will be around 0V. T3 will therefore be turned off and the external pull up resistor REXT will pull the collector voltage of T3 up to +V, which will be at the valid logic 1 level of the next gate.

 

                       Open Collector Gates Electrical Engineering (EE) Notes | EduRev
                     Fig. 3.4.1 Simplified circuit of an Open Collector NAND Gate

 

Logic Level Translation

Open collector and open drain gates can therefore be used for changing the levels of an output to match the higher or lower logic levels of an input on a different family of gates, when gates of mixed families are used.

Open collector gates can be used with external collector VCC supplies having a voltage typically somewhere between +1.5V to +5.5V for logic gates, Buffer ICs are also available that can operate on collector VCC supplies up to +30V. The maximum value of collector voltage is set by the VOH parameter of the open collector gate.

 

Wired Logic Functions

Open collector ICs are available in most of the logic types, AND, NAND etc, with the exception of OR gates. However open collector gates can be used to make both wired AND and wired OR functions as shown in Figs. 3.4.2 and 3.4.3. The outputs of gates without open collectors must not be connected together, because if the outputs happen to be at opposite logic states, the gate with a logic 0 output will try to sink more current than the logic 1 gate can source, and damage will most probably occur. However with open collector (or drain) gates, a gate output at logic 0 will be sinking current drawn from the external pull up resistor REXT, and any other connected open collector gate trying to output a logic 1 will have its output transistor turned off and so will not be sourcing any current.

 

                     Open Collector Gates Electrical Engineering (EE) Notes | EduRev

 

Wired AND

If two or more open collector gate outputs are connected together, any gate with a logic 0 output will pull all other connected outputs to logic 0, giving an output of logic 0 at output X, but if all the connected outputs are at logic 1, then X will be at logic 1, the action of an ‘invisible’ AND gate.

 

Wired OR

It is also possible to implement a wired OR function using open collector (or drain) gates as shown in Fig. 3.4.3, although the explanation here is a little more complex as it involves using Negative Logic.

The circuit in Fig. 3.4.3 is used to obtain the Boolean function (A•B)+(C•D) without using a physical OR gate.

Notice that the circuit in Fig. 3.4.3 is similar to the wired AND circuit in Fig. 3.4.2, except that the two open collector AND gates have been replaced by two open collector NAND gates. The main difference with this circuit however is that to obtain an OR function from what appears to be a wired AND function, Negative Logic is applied.

 

       Open Collector Gates Electrical Engineering (EE) Notes | EduRev

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