PPT: Memory System | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) PDF Download

 Page 1


The Memory System
Page 2


The Memory System
Overview
l Basic memory circuits
l Organization of the main memory
l Cache memory concept
l Virtual memory mechanism
l Secondary storage
Page 3


The Memory System
Overview
l Basic memory circuits
l Organization of the main memory
l Cache memory concept
l Virtual memory mechanism
l Secondary storage
Basic Concepts
l The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
16-bit addresses = 2
16
= 64K memory locations
l Most modern computers are byte addressable.
2
k
4 - 2
k
3 - 2
k
2 - 2
k
1 - 2
k
4 - 2
k
4 -
0 1 2 3
4 5 6 7
0 0
4
2
k
1 - 2
k
2 - 2
k
3 - 2
k
4 -
3 2 1 0
7 6 5 4
Byte address Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
Word
address






Page 4


The Memory System
Overview
l Basic memory circuits
l Organization of the main memory
l Cache memory concept
l Virtual memory mechanism
l Secondary storage
Basic Concepts
l The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
16-bit addresses = 2
16
= 64K memory locations
l Most modern computers are byte addressable.
2
k
4 - 2
k
3 - 2
k
2 - 2
k
1 - 2
k
4 - 2
k
4 -
0 1 2 3
4 5 6 7
0 0
4
2
k
1 - 2
k
2 - 2
k
3 - 2
k
4 -
3 2 1 0
7 6 5 4
Byte address Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
Word
address






Traditional Architecture
Up to 2
k
addressable
MDR
MAR
Figure 5.1. Connection of the memory to the processor.
k-bit
address bus
n-bit
data bus
Control lines
(          , MFC, etc.)
Processor
Memory
locations
Word length =n bits
W R/
Page 5


The Memory System
Overview
l Basic memory circuits
l Organization of the main memory
l Cache memory concept
l Virtual memory mechanism
l Secondary storage
Basic Concepts
l The maximum size of the memory that can be used in any computer is
determined by the addressing scheme.
16-bit addresses = 2
16
= 64K memory locations
l Most modern computers are byte addressable.
2
k
4 - 2
k
3 - 2
k
2 - 2
k
1 - 2
k
4 - 2
k
4 -
0 1 2 3
4 5 6 7
0 0
4
2
k
1 - 2
k
2 - 2
k
3 - 2
k
4 -
3 2 1 0
7 6 5 4
Byte address Byte address
(a) Big-endian assignment (b) Little-endian assignment
4
Word
address






Traditional Architecture
Up to 2
k
addressable
MDR
MAR
Figure 5.1. Connection of the memory to the processor.
k-bit
address bus
n-bit
data bus
Control lines
(          , MFC, etc.)
Processor
Memory
locations
Word length =n bits
W R/
Basic Concepts
l“Block transfer” – bulk data transfer
l Memory access time
l Memory cycle time
l RAM – any location can be accessed for a
Read or Write operation in some fixed
amount of time that is independent of the
location’s address.
l Cache memory
l Virtual memory, memory management unit