8086 Processor Family
The x86 organization has evolved dramatically over the years.
Register Organization :
The register organization includes the following types of registers (Table 3.1):
There are eight 32-bit general-purpose registers. These may be used for all types of x86 instructions; and some of these registers also serve special purposes. For example, string instructions use the contents of the ECX, ESI, and EDI registers as operands without having to reference these registers explicitly in the instruction.
The six 16-bit segment registers contain segment selectors, which index into segment tables, as discussed in Chapter 8. The code segment (CS) register references the segment containing the instruction being executed. The stack segment (SS) register references the segment containing a uservisible stack.The remaining segment registers (DS,ES,FS,GS) enable the user to reference up to four separate data segments at a time.
The 32-bit EFLAGS register contains condition codes and various mode bits. In 64-bit mode, this register is extended to 64 bits and referred to as RFLAGS. In the current architecture definition, the upper 32 bits of RFLAGS are unused.
• Instruction pointer:
Contains the address of the current instruction. There are also registers specifically devoted to the floating-point unit:
Each register holds an extended-precision 80-bit floating-point number. There are eight registers that function as a stack, with push and pop operations available in the instruction set.
The 16-bit control register contains bits that control the operation of the floating-point unit, including the type of rounding control; single, double, or extended precision; and bits to enable or disable various exception conditions.
The 16-bit status register contains bits that reflect the current state of the floating-point unit, including a 3-bit pointer to the top of the stack; condition codes reporting the outcome of the last operation; and exception flags.
• Tag word:
This 16-bit register contains a 2-bit tag for each floating-point numeric register, which indicates the nature of the contents of the corresponding register. The four possible values are valid, zero, special (NaN, infinity, denormalized),and empty.
The EFLAGS register (Figure 3.9) indicates the condition of the processor and helps to control its operation. It includes the six condition codes (carry, parity, auxiliary, zero, sign, overflow), which report the results of an integer operation. In addition, there are bits in the register that may be referred to as control bits:
• Trap flag (TF):
When set, causes an interrupt after the execution of each instruction. This is used for debugging.
• Interrupt enable flag (IF):
When set, the processor will recognize external interrupts.
• Direction flag (DF):
Determines whether string processing instructions increment or decrement the 16-bit half-registers SI and DI (for 16-bit operations) or the 32-bit registers ESI and EDI (for 32-bit operations).
• I/O privilege flag (IOPL):
When set, causes the processor to generate an exception on all accesses to I/O devices during protected-mode operation.
• Resume flag (RF): Allows the programmer to disable debug exceptions so that the instruction can be restarted after a debug exception without immediately causing another debug exception.
• Alignment check (AC): Activates if a word or doubleword is addressed on a nonword or nondoubleword boundary.
• Identification flag (ID):
If this bit can be set and cleared, then this processor supports the processorID instruction. This instruction provides information about the vendor, family, and model.
• Nested Task (NT)
flag indicates that the current task is nested within another task in protectedmode operation.
• Virtual Mode (VM)
bit allows the programmer to enable or disable virtual 8086 mode, which determines whether the processor runs as an 8086 machine.
• Virtual Interrupt Flag (VIF)
and Virtual Interrupt Pending (VIP) flag are used in a multitasking environment
The x86 employs four control registers (register CR1 is unused) to control various aspects of processor operation . All of the registers except CR0 are either 32 bits or 64 bits long..The flags are are as follows:
• Protection Enable (PE):
Enable/disable protected mode of operation.
• Monitor Coprocessor (MP):
Only of interest when running programs from earlier machines on the x86; it relates to the presence of an arithmetic coprocessor.
• Emulation (EM):
Set when the processor does not have a floating-point unit, and causes an interrupt when an attempt is made to execute floating-point instructions.
• Task Switched (TS):
Indicates that the processor has switched tasks.
• Extension Type (ET):
Not used on the Pentium and later machines; used to indicate support of math coprocessor instructions on earlier machines.
• Numeric Error (NE):
Enables the standard mechanism for reporting floating-point errors on external bus lines.
• Write Protect (WP):
When this bit is clear, read-only user-level pages can be written by a supervisor process. This feature is useful for supporting process creation in some operating systems.
• Alignment Mask (AM):
Enables/disables alignment checking.
• Not Write Through (NW):
Selects mode of operation of the data cache. When this bit is set, the data cache is inhibited from cache write-through operations.
• Cache Disable (CD):
Enables/disables the internal cache fill mechanism.
• Paging (PG):
1. When paging is enabled, the CR2 and CR3 registers are valid.
2. The CR2 register holds the 32-bit linear address of the last page accessed before a page fault interrupt.
3. The leftmost 20 bits of CR3 hold the 20 most significant bits of the base address of the page directory; the remainder of the address contains zeros. The page-level cache disable (PCD) enables or disables the external cache, and the page-level writes transparent (PWT) bit controls write through in the external cache.
4. Nine additional control bits are defined in CR4:
• Virtual-8086 Mode Extension (VME):
Enables virtual interrupt flag in virtual-8086 mode.
• Protected-mode Virtual Interrupts (PVI):
Enables virtual interrupt flag in protected mode.
• Time Stamp Disable (TSD):
Disables the read from time stamp counter (RDTSC) instruction, which is used for debugging purposes.
• Debugging Extensions (DE):
Enables I/O breakpoints; this allows the processor to interrupt on I/O reads and writes.
• Page Size Extensions (PSE):
Enables large page sizes (2 or 4-MByte pages) when set; restricts pages to 4 KBytes when clear.
• Physical Address Extension (PAE):
Enables address lines A35 through A32 whenever a special new addressing mode, controlled by the PSE, is enabled.
• Machine Check Enable (MCE):
Enables the machine check interrupt, which occurs when a data parity error occurs during a read bus cycle or when a bus cycle is not successfully complete
• Page Global Enable (PGE):
Enables the use of global pages. When PGE = 1 and a task switch is performed, all of the TLB entries are flushed with the exception of those marked global.
• Performance Counter Enable(PCE):
Enables the Execution of the RDPMC (read performance counter) instruction at any privilege level.
The MMX instructions make use of 3-bit register address fields, so that eight MMX registers are supported. (Figure 3.11). The existing floating-point registers are used to store MMX values. Specifically, the low-order 64 bits (mantissa) of each floating-point register are used to form the eight MMX registers. Some key characteristics of the MMX use of these registers are as follows: