Previous Year Questions- Logic Families and Miscellaneous | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Q1: The logical gate implemented using the circuit shown below where, V₁ and V₂ are inputs (with 0 V as digital 0 and 5 V as digital 1) and  V_OUT is the output is (SET-1(2017))(a) NOT
(b) NOR
(c) NAND
(d) XOR
Ans: (b)
Sol: When V₁ = high 5 V,  Q₁ on, V_out = 0
 V₂ = high 5 V, Q₂ on, V_out = 0
Thus when any V₁ or V₂ is high then, V_out = 0
⇒
Thus, it is a NOR gate.

Q2: In the circuit shown below,  Q₁ has negligible collector-to-emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If V_cc is +5 V, X and Y are digital signals with 0 V as logic 0 and V_cc as logic 1, then the Boolean expression for Z is  (2013)
(a) XY
(b)
(c)
(d)
Ans: (b)
Sol: ⇒

Q3: The TTL circuit shown in the figure is fed with the waveform X (also shown). All gates have equal propagation delay of 10 ns. The output Y of the circuit is (2010)
(a) (b) (c) (d) Ans: (a)
Sol: 
Q4: A TTL NOT gate circuit is shown in figure. Assuming V_BE = 0.7 V of both the transistors, if  V_i = 3.0 V, then the states of the two transistors will be (2006)
(a) Q₁ ON and Q₂ OFF
(b) Q₁ reverse ON and Q₂ OFF
(c) $Q1$Q₁ reverse ON and Q₂ ON
(d) Q₁ OFF and Q₂ reverse ON
Ans: (c)
Sol: When V_i = 3V then Q₁ will be in reverse active mode i.e. reverse ON and Q₂ will be ON.

Q5: If X₁ and X₂ are the inputs to the circuit shown in the figure, the output Q is (2005)
(a)
(b)
(c)
(d)
Ans: (d)
Sol: Output,