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SRAM and DRAM Peripherals - Electrical Engineering (EE) PDF Download

Objectives

 In this lecture you will learn the following

  • Introduction
  •  
  • SRAM and its Peripherals
  • DRAM and its Peripherals

 

30.1 Introduction

Even though a lot of the concepts here have been discussed earlier, they are repeated for convenience

Broadly memories can be classified into

  • RAM (Random Access Memory)
  • Serial Memory

A RAM is one in which the time required for accessing the information and retrieving the information is independent of the physical location of the information. In contrast, in a Serial memory, the data is available only in the same form as it was stored previously.

The following diagram shows the organization of a Memory

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.11: Organization of Memory

This memory consists of two address decoders viz. Row and Column decoders to select a particular bit in the memory. If there are M rows and N columns, then the number of bits that can be accessed are SRAM and DRAM Peripherals - Electrical Engineering (EE)  Either a read operation or a writeoperation can be done on any selected bit by the use of control signals.

RAMs are once again classified into two types:

  • SRAM (Static RAM)
  • DRAM (Dynamic RAM)


30.2 SRAM And Its Peripherals

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.21: SRAM Cell

 

Figure 30.21 shows a standard 6 transistor SRAM cell. The signal designed as WL is the WORDLINE used to read or write into the cell. BL  and SRAM and DRAM Peripherals - Electrical Engineering (EE) are the data to be written into the cell.

SRAM and DRAM Peripherals - Electrical Engineering (EE)

 

 

Fig 30.22: Circuit for reading and writing data into cell

The circuits shown in the previous page are used to write and read the data to and from the cell. When a read operation is to be performed, RW  signal is made HIGH and at the same time   SRAM and DRAM Peripherals - Electrical Engineering (EE) is made LOW. As a result the data present on the BIT and SRAM and DRAM Peripherals - Electrical Engineering (EE)lines are transferred to the input of the sense amplifier (Sense amplifier operation will be discussed shortly). The sense amplifier then senses the data and gives the output.

During the write operation, RW, is made LOW and SRAM and DRAM Peripherals - Electrical Engineering (EE) is made HIGH. Thus the DATA and SRAM and DRAM Peripherals - Electrical Engineering (EE) will be written onto the BIT and SRAM and DRAM Peripherals - Electrical Engineering (EE)  lines respectively.

However the read and write operation on a particular cell takes place only if the cell is enabled by the corresponding row(Word) and column(Digit) lines. It is important to remember that before every read operation, the  BIT and SRAM and DRAM Peripherals - Electrical Engineering (EE)  are precharged to a voltage (usually VDD/2). During read operation, one of the two BIT ( SRAM and DRAM Peripherals - Electrical Engineering (EE) or SRAM and DRAM Peripherals - Electrical Engineering (EE)) lines discharges slightly whereas the other line charges to a voltage slightly greater than its precharged value. This difference in these voltages is detected by the sense amplifier to produce and output voltage, which corresponds to te stored value in the cell which is read. Care should be taken in sizing the transistors to ensure that the data stored in the cell does not change its value.

 

30.3 Sense Amplifier

The circuit shown in Figure 30.31 is the sense amplifier used to read data from the cell. As soon as the SE signal goes HIGH the amplifier senses the difference between the SRAM and DRAM Peripherals - Electrical Engineering (EE) and SRAM and DRAM Peripherals - Electrical Engineering (EE)voltages and produces an output voltage appropriately. The access time of the memory, which is defined as the time between the initiation of the read operation and the appearance of the output, mainly depends on the performance of the sense amplifier. So the design of the sense amplifier forms the main criteria for the design of memories. The one that is shown here is a simple sense amplifier.

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.31: Differential Sense Amplifier

Figure 30.31 shows the block diagram of a memory cell with all the peripherals

 

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.32: Block Diagram Of A Memory Cell With All Its Peripherals

 

30.4 Another Type of Sensing

 

SRAM and DRAM Peripherals - Electrical Engineering (EE)

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.41: SRAM Sensing Scheme

In the above figure, SRAM and DRAM Peripherals - Electrical Engineering (EE) is the signal used to precharge the BIT and B lines before every read operation. The transistor labelled EQ is the equalization transistor to ensure equal voltages on BIT long and SRAM and DRAM Peripherals - Electrical Engineering (EE)lines after precharge. SE is the sense enable signal used to sense the voltage difference between the SRAM and DRAM Peripherals - Electrical Engineering (EE)and SRAM and DRAM Peripherals - Electrical Engineering (EE)lines.

 

SRAM and DRAM Peripherals - Electrical Engineering (EE)

SRAM and DRAM Peripherals - Electrical Engineering (EE)

Fig 30.42: Two Stage Differential Amplifier

 

As mentioned earlier, the access time of the memory mainly depends on the performance of the sense amplifier. In contrast with the simple sense amplifier shown earlier, Figure 30.42 shows an amplifier which is somewhat complicated to improve the performance.

 

30.5 DRAM And Its Peripherals

 

The circuit shown in Figure 30.51 is the simple DRAM circuit. Charge sharing takes place between the two capacitors during read and write operations in the following manner. During the write cycle, Cs is charged or discharged by asserting WL and BL. During the read cycle, charge redistribution takes place between the bit line and the storage capacitance.

SRAM and DRAM Peripherals - Electrical Engineering (EE)            (Eq 30.1)

 

Voltage swing is small; typically around 250mV.

Figure 30.52 shows a simple 3-transistor DRAM cell.

 

SRAM and DRAM Peripherals - Electrical Engineering (EE)

SRAM and DRAM Peripherals - Electrical Engineering (EE)

SRAM and DRAM Peripherals - Electrical Engineering (EE)

 

Fig 30.52: 3-Transistor DRAM Cell

Figure 30.53 shows a very simple address decoder. These address decoders are compulsory in case of main memories. But the cache memories avoid the usage of address decoders. Many other possible architectures are available for address decoding.

SRAM and DRAM Peripherals - Electrical Engineering (EE)

 

Fig 30.53: A Simple Address Decoder

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FAQs on SRAM and DRAM Peripherals - Electrical Engineering (EE)

1. What is the difference between SRAM and DRAM?
Ans. SRAM (Static Random-Access Memory) and DRAM (Dynamic Random-Access Memory) are two different types of memory used in computer systems. The main difference between them is the way they store data. SRAM uses flip-flops to store data, which makes it faster but more expensive and less dense than DRAM. On the other hand, DRAM stores data in capacitors, which makes it slower but cheaper and more dense than SRAM.
2. How does SRAM work?
Ans. SRAM works by using flip-flops to store data. A flip-flop is a circuit composed of gates that can hold a single bit of data in a stable state. SRAM consists of multiple flip-flops organized in a matrix-like structure. Each flip-flop represents a memory cell that can store a bit of data. When data needs to be read or written, the appropriate address is provided, and the stored data is accessed directly from the flip-flops.
3. How does DRAM work?
Ans. DRAM works by storing data in capacitors. Each memory cell in a DRAM chip consists of a capacitor and a transistor. The capacitor stores a charge that represents the data bit (0 or 1). To read the data, the transistor is used to access the charge stored in the capacitor. However, due to the nature of capacitors, the stored charge gradually leaks away. Therefore, DRAM requires constant refreshing to maintain the data integrity, which makes it slower compared to SRAM.
4. Which memory type is more commonly used in modern computers?
Ans. DRAM is more commonly used in modern computers due to its higher density and lower cost per bit. It allows for more memory to be packed into a smaller physical space, making it suitable for applications that require large amounts of memory, such as system memory (RAM). SRAM, on the other hand, is used in cache memory, which is faster but more expensive and has lower capacity compared to DRAM.
5. What are some advantages of SRAM over DRAM?
Ans. Some advantages of SRAM over DRAM include faster access times, lower power consumption, and no need for constant refreshing. SRAM can operate at higher clock speeds, making it ideal for cache memory, which requires quick access to frequently used data. Additionally, SRAM does not need to constantly refresh the stored data like DRAM, which saves power. However, SRAM is more expensive, less dense, and has lower capacity compared to DRAM.
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