Small Signals Modeling of BJT and their Analysis (Part - 1) - Electrical Engineering (EE) PDF Download

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Transistor switching networks: Through proper design transistors can be used as switches for computer and control applications.
When the input voltage V_B is high ( logic 1), the transistor is in saturation ( ON). And the output at its collector = V_CE is almost 0V( Logic 0)

Transistor as a switch
When the base voltage V_B is low( logic 0), i.e, 0V, the transistor is cutoff( Off) and I_C is 0, drop across R_C is 0 and therefore voltage at the collector is V_CC.( logic 1) Thus transistor switch operates as an inverter.
This circuit does not require any DC bias at the base of the transistor.

Design
When V_i ( V_B) is 5V, transistor is in saturation and I_Csat Just before saturation, I_B,_max = I_C,_sat / βD_C Thus the base current must be greater than I_B,_max to make the transistor to work in saturation.
 

Analysis

When V_i = 5V, the resulting level of I_B is

I_B = (V_i – 0.7) / R_B

= ( 5 – 0.7) / 68k = 63mA 
I_Csat = V_CC / R_C = 5/0.82k = 6.1mA
 

Verification

( I_C,sat / β) = 48.8mA

Thus I_B > ( I_C,sat / β)  which is required for a transistor to be in saturation.

A transistor can be replaced by a low resistance Rsat when in saturation ( switch on) Rsat = V_{CE sat}/ ICsat (V_{CE sat} is very small and I_Csat is I_C,_max is maximum current)

A transistor can be replaced by a high resistance Rcutoff when in cutoff ( switch on)

Problem 

Determine R_B and R_C for the inverter of figure:

I_{C sat} = V_CC / R_C
10mA = 10V/ R_C
R_C = 1kΩ
I_B just at saturation = I_{C sat} / β = 10mA / 250 = 40μA 
Choose I_B> I_{C sat} / β, 60 μA I_B = (V_i - 0.7) / R_B 60 mA = ( 10 - 0.7) / R_B
R_B = 155kΩ
Choose R_B = 150kΩ, standard value, recalculate I_B, we get I_B = 62 μA
which is also >  I_{C sat} / β Thus, R_C = 1k and R_B = 155k
 

Switching Transistors 

Transistor „ON‟ time = delay time + Rise time Delay time is the time between the changing state of the input and the beginning of a response at the output.
Rise time is the time from 10% to 90% of the final value.
Transistor „OFF‟ time = Storage time + Fall time
For an „ON‟ transistor, V_BE should be around 0.7V
For the transistor to be in active region, V_CE is usually about 25% to 75% of V_CC. If V_CE = almost V_CC, probable faults:
– the device is damaged
– connection in the collector – emitter or base – emitter circuit loop is open.
One of the most common mistake in the lab is usage of wrong resistor value. Check various voltages with respect to ground.
Calculate the current values using voltage readings rather than measuring current by breaking the circuit.

Problem – 1
Check the fault in the circuit given.

Problem - 2

PNP transistors

The analysis of PNP transistors follows the same pattern established for NPN transistors. The only difference between the resulting equations for a network in which an npn transistor has been replaced by a pnp transistor is the sign associated with particular quantities.

PNP transistor in an emitter bias

Applying KVL to Input loop:

V_CC = I_BR_B +V_BE+I_ER_E
Thus, I_B = (V_CC – V_BE) / [R_B + (β+1) R_E]
Applying KVL Output loop: V_CE = - ( V_CC - I_CR_C)

Bias stabilization

The stability of a system is a measure of the sensitivity of a network to variations in its parameters.
In any amplifier employing a transistor the collector current I_C is sensitive to each of the following parameters. b increases with increase in temperature.
Magnitude of V_BE decreases about 2.5mV per degree Celsius increase in temperature. I_CO doubles in value for every 10 degree Celsius increase in temperature.

Stability factors

S (I_CO) = ΔI_C / ΔI_C0
S (V_BE) = ΔI_C / ΔV_BE
S (β) = ΔI_C / Δ β
Networks that are quite stable and relatively insensitive to temperature variations have low stability factors.
The higher the stability factor, the more sensitive is the network to variations in that parameter.

S( I_CO)

•  Analyze S( I_CO) for
  – emitter bias configuration
  – fixed bias configuration
  – Voltage divider configuration

For the emitter bias configuration,

S( I_CO) = ( β + 1) [ 1 + R_B / R_E] / [( β + 1) + R_B / 

R_E] If R_B / R_E >> ( β + 1) ,

then S( I_CO) = ( β + 1)

For R_B / R_E <<1, S( I_CO) 1

Thus, emitter bias configuration is quite stable when the ratio R_B / R_E is as small as possible.
Emitter bias configuration is least stable when R_B / R_E approaches ( β + 1) .

Fixed bias configuration 

S( ICO) = ( β + 1) [ 1 + R_B / R_E] / [( β + 1) + R_B / 
R_E] = ( β + 1) [R_E + R_B] / [( β + 1) R_E + R_B]
By plugging R_E = 0, we get S( I_CO) = β + 1
This indicates poor stability.

Voltage divider configuration

S( I_CO) = ( β + 1) [ 1 + R_B / R_E] / [( β + 1) + R_B / 
R_E] Here, replace R_B with R_th S( I_CO) = ( β + 1) [ 1 + R_th / R_E] /  [( β + 1)  + R_th / R_E]
Thus, voltage divider bias configuration is quite stable when the ratio R_th / R_E is as small as possible.

Physical impact

In a fixed bias circuit, I_C increases due to increase in I_C0. [I_C = βI_B + (β+1) I_C0] I_B is fixed by V_CC and R_B. Thus level of I_C would continue to rise with temperature - a very unstable situation.
In emitter bias circuit, as I_C increases, I_E increases, V_E increases. Increase in V_E reduces I_B. I_B = [V_CC – V_BE – V_E] / R_B. A drop in I_B reduces I_C.Thus, this configuration is such that there is a reaction to an increase in I_C that will tend to oppose the change in bias conditions.
In the DC bias with voltage feedback, as I_C increases, voltage across R_C increases, thus reducing I_B and causing I_C to reduce.
The most stable configuration is the voltage – divider network. If the condition βR_E >>10R₂, the voltage V_B will remain fairly constant for changing levels of I_C. V_BE = V_B - V_E, as I_C increases, V_E increases, since V_B is constant, V_BE drops making I_B to fall, which will try to offset the increases level of I_C.
S(V_BE)
S(V_BE) = ΔI_C / ΔV_BE
For an emitter bias circuit,  S(V_BE) = - β / [ R_B + (β + 1)R_E]
If R_E =0 in the above equation, we get S(V_BE) for a fixed bias circuit as, S(V_BE) = - β / R_B.

For an emitter bias,
S(VBE) = - β / [ R_B + (β + 1)R_E] can be rewritten as, S(V_BE) = - (β/R_E )/ [R_B/R_E + (β + 1)]
If (β + 1)>> R_B/R_E, then S(V_BE) = - (β/R_E )/ (β + 
1) = - 1/ R_E
The larger the R_E, lower the S(V_BE) and more stable is the system.
Total effect of all the three parameters on I_C can be written as,

ΔI_C = S(I_CO) ΔI_CO + S(V_BE) ΔV_BE + S(β)Δβ

General conclusion: The ratio R_B / R_E or R_th / R_E should be as small as possible considering all aspects of design.
 

Transistor at low frequencies

• Introduction
• Amplification in the AC domain
• BJT transistor modeling
• The re Transistor Model
• The Hybrid equivalent Model 

Introduction

• There are three models commonly used in the small – signal ac analysis of transistor networks:
• The re model
• The hybrid p model
• The hybrid equivalent model

Amplification in the AC domain

The transistor can be employed as an amplifying device, that is, the output ac power is greater than the input ac power. The factor that permits an ac power output greater than the input ac power is the applied DC power. The amplifier is initially biased for the required DC voltages and currents. Then the ac to be amplified is given as input to the amplifier. If the applied ac exceeds the limit set by dc level, clipping of the peak region will result in the output. Thus, proper (faithful) amplification design requires that the dc and ac components be sensitive to each other‟s requirements and limitations. The superposition theorem is applicable for the analysis and design of the dc and ac components of a BJT network, permitting the separation of the analysis of the dc and ac responses of the system.

BJT Transistor modeling

• The key to transistor small-signal analysis is the use of the equivalent circuits (models). A MODEL IS A COMBINATION OF CIRCUIT ELEMENTS LIKE VOLTAGE OR CURRENT SOURCES, RESISTORS, CAPACITORS  etc, that best approximates the behavior of a device under specific operating conditions. Once the model (ac equivalent circuit) is determined, the schematic symbol for the device can be replaced by the equivalent circuit and the basic methods of circuit analysis applied to determine the desired quantities of the network.
• Hybrid equivalent network – employed initially.
  Drawback – It is defined for a set of operating conditions that might not match the actual operating conditions.
• re model: desirable, but does not include feedback term 
• Hybrid p model: model of choice. 

AC equivalent of a network 

• AC equivalent of a network is obtained by:
• Setting all dc sources to zero and replacing them by a short – circuit equivalent
• Replacing all capacitors by short – circuit equivalent
• Removing all elements bypassed by the short – circuit equivalents
• Redrawing the network in a more convenient and logical form.

r_e model

• In r_e model, the transistor action has been replaced by a single diode between emitter and base terminals and a controlled current source between base and collector terminals.
• This is rather a simple equivalent circuit for a device