Synchronous Counters Electrical Engineering (EE) Notes | EduRev

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Electrical Engineering (EE) : Synchronous Counters Electrical Engineering (EE) Notes | EduRev

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Synchronous Counters

The synchronous counter provides a more reliable circuit for counting purposes, and for high-speed operation, as the clock pulses in this circuit are fed to every flip-flop in the chain at exactly the same time. Synchronous counters use JK flip-flops, as the programmable J and K inputs allow the toggling of individual flip-flops to be enabled or disabled at various stages of the count. Synchronous counters therefore eliminate the clock ripple problem, as the operation of the circuit is synchronised to the CK pulses, rather than flip-flop outputs.

 

Synchronous Up Counter

Fig. 5.6.5 shows how the clock pulses are applied in a synchronous counter. Notice that the CK input is applied to all the flip-flops in parallel. Therefore, as all the flip-flops receive a clock pulse at the same instant, some method must be used to prevent all the flip-flops changing state at the same time. This of course would result in the counter outputs simply toggling from all ones to all zeros, and back again with each clock pulse.

However, with JK flip-flops, when both J and K inputs are logic 1 the output toggles on each CK pulse, but when J and K are both at logic 0 no change takes place.

   Synchronous Counters Electrical Engineering (EE) Notes | EduRev

Fig. 5.6.6 shows two stages of a synchronous counter. The binary output is taken from the Q outputs of the flip-flops. Note that on FF0 the J and K inputs are permanently wired to logic 1, so Q0 will change state (toggle) on each clock pulse. This provides the ‘ones’ count for the least significant bit.

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

On FF1 the J1 and K1 inputs are both connected to Q0so that FF1 output will only be in toggle mode when Q0is also at logic 1. As this only happens on alternate clock pulses, Q1 will only toggle on even numbered clock pulses giving a ‘twos’ count on the Q1 output.

 

Table 5.6.1 shows this action, where it can be seen that Q1 toggles on the clock pulse only when J1 and K1 are high, giving a two bit binary count on the Q outputs, (where Q0 is the least significant bit).

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

In adding a third flip flop to the counter however, direct connection from J and K to the previous Q1 output would not give the correct count. Because Q1 is high at a count of 210 this would mean that FF2 would toggle on clock pulse three, as J2 and K2 would be high. Therefore clock pulse 3 would give a binary count of 1112 or 710 instead of 410.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

To prevent this problem an AND gate is used, as shown in Fig. 5.6.7 to ensure that J2 and K2 are high only when both Q0 and Q1 are at logic 1 (i.e. at a count of three). Only when the outputs are in this state will the next clock pulse toggle Q2 to logic 1. The outputs Q0 and Q1 will of course return to logic 0 on this pulse, so giving a count of 0012 or 410 (with Q0 being the least significant bit).

 

 

Fig. 5.6.8 shows the additional gating for a four stage synchronous counter. Here FF3 is put into toggle mode by making J3 and K3 logic 1, only when Q0 Q1 and Q2 are all at logic 1.

Q3 therefore will not toggle to its high state until the eighth clock pulse, and will remain high until the sixteenth clock pulse. After this pulse, all the Q outputs will return to zero.

Note that for this basic form of the synchronous counter to work, the Synchronous Counters Electrical Engineering (EE) Notes | EduRev inputs must also be all at logic 1, (their inactive state) as shown in Fig. 5.6.8.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

Synchronous Down Counter

Converting the synchronous up counter to count down is simply a matter of reversing the count. If all of the ones and zeros in the 0 to 1510 sequence shown in Table 5.6.2 are complemented, (shown with a pink background) the sequence becomes 1510to 0.
 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev 

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev 

 

Down Counter Circuit

As every Q output on the JK flip-flops has its complement on Synchronous Counters Electrical Engineering (EE) Notes | EduRev, all that is needed to convert the up counter in Fig. 5.6.8 to the down counter shown in Fig 5.6.9 is to take the JK inputs for FF1 from the Q output of FF0 instead of the Synchronous Counters Electrical Engineering (EE) Notes | EduRev output. Gate TC2 now takes its inputs from the Synchronous Counters Electrical Engineering (EE) Notes | EduRev outputs of FF0 and FF1, and TC3 also takes its input from FF2 Synchronous Counters Electrical Engineering (EE) Notes | EduRev output.

 

Up/Down Counter

Fig. 5.6.10 illustrates how a single input, called Synchronous Counters Electrical Engineering (EE) Notes | EduRev can be used to make a single counter count either up or down, depending on the logic state at the Synchronous Counters Electrical Engineering (EE) Notes | EduRev input. 

Each group of gates between successive flip-flops is in fact a modified data select circuit described in Combinational Logic Module 4.2 but in this version an AND/OR combination is used in preference to its DeMorgan equivalent NAND gate circuitThis is necessary to provide the correct logic state for the next data selector.

The Q and Synchronous Counters Electrical Engineering (EE) Notes | EduRev outputs of flip-flops FF0, FF1 and FF2 are connected to what are, in effect, the A and B data inputs of the data selectors. If the control input is at logic 1 then the CK pulse to the next flip-flop is fed from the Q output, making the counter an UP counter, but if the control input is 0 then CK pulses are fed from Synchronous Counters Electrical Engineering (EE) Notes | EduRev and the counter is a DOWN counter.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

Synchronous BCD Up Counter

A typical use of the Synchronous Counters Electrical Engineering (EE) Notes | EduRev inputs is illustrated in the BCD Up Counter in Fig 5.6.11. The counter outputs Q1 and Q3 are connected to the inputs of a NAND gate, the output of which is taken to the Synchronous Counters Electrical Engineering (EE) Notes | EduRev inputs of all four flip-flops. When Q1 and Q3are both at logic 1, the output terminal of the limit detection NAND gate (LD1) will become logic 0 and reset all the flip-flop outputs to logic 0.

Because the first time Q1 and Q3 are both at logic 1 during a 0 to 1510 count is at a count of ten (10102), this will cause the counter to count from 0 to 910 and then reset to 0, omitting 1010 to 1510.

The circuit is therefore a BCD8421 counter, an extremely useful device for driving numeric displays via a BCD to 7-segment decoder etc. However by re-designing the gating system to produce logic 0 at the Synchronous Counters Electrical Engineering (EE) Notes | EduRev inputs for a different maximum value, any count other than 0 to 15 can be achieved.

If you already have a simulator such as Logisim installed on your computer, why not try designing an Octal up counter for example.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

Counter IC Inputs and Outputs

Although synchronous counters can be, and are built from individual JK flip-flops, in many circuits they will be ether built into dedicated counter ICs, or into other large scale integrated circuits (LSICs).

For many applications the counters contained within ICs have extra inputs and outputs added to increase the counters versatility. The differences between many commercial counter ICs are basically the different input and output facilities offered. Some of which are described below. Notice that many of these inputs are active low; this derives from the fact that in earlier TTL devices any unconnected input would float up to logic 1 and hence become inactive. However leaving inputs un-connected is not good practice, especially CMOS inputs, which float between logic states, and could easily be activated to either valid logic state by random noise in the circuit, therefore ANY unused input should be permanently connected to its inactive logic state.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

 

 Enable Inputs

ENABLESynchronous Counters Electrical Engineering (EE) Notes | EduRev inputs on counter ICs may have a number of different names, e.g. Chip Enable Synchronous Counters Electrical Engineering (EE) Notes | EduRev, Count Enable Synchronous Counters Electrical Engineering (EE) Notes | EduRev, Output Enable Synchronous Counters Electrical Engineering (EE) Notes | EduRev etc., each denoting the same or similar functions.

Count Enable Synchronous Counters Electrical Engineering (EE) Notes | EduRev for example, is a feature on counter integrated circuits, and in the synchronous counter illustrated in Fig 5.6.13, is an active low input. When it is set to logic 1, it will prevent the count from progressing, even in the presence of clock pulses, but the count will continue normally when Synchronous Counters Electrical Engineering (EE) Notes | EduRev is at logic 0.

A common way of disabling the counter, whilst retaining any current data on the Q outputs, is to inhibit the toggle action of the JK flip-flops whilst Synchronous Counters Electrical Engineering (EE) Notes | EduRev is inactive (logic 1), by making the JK inputs of all the flip-flops logic 0. However, as the logic states of the JK inputs of FF1, FF2 and FF3 depend on the state of the previous Q output, either directly or via gates T2 and T3, in order to preserve the output data, the Q outputs must be isolated from the JK inputs whenever Synchronous Counters Electrical Engineering (EE) Notes | EduRev is logic 1, but the Q outputs must connect to the JK inputs when Synchronous Counters Electrical Engineering (EE) Notes | EduRev is at logic 0 (the count enabled state).

This is achieved by using the extra (AND) enable gates, E1, E2 and E3, each of which have one of their inputs connected to CTEN (the inverse of Synchronous Counters Electrical Engineering (EE) Notes | EduRev. When the count is disabled, CTEN and therefore one of the inputs on each of , E1, E2 and E3 will be at logic 0, which will cause these enable gate outputs, and the flip-flop JK inputs to also be at logic 0, whatever logic states are present on the Q outputs, and also at the other enable gate inputs. Therefore whenever CTEN is at logic 1 the count is disabled.

When Synchronous Counters Electrical Engineering (EE) Notes | EduRev is at logic 0 however, CTEN will be logic 1 and E1, E2 and E3 will be enabled, causing whatever logic state is present on the Q outputs to be passed to the JK inputs. In this condition, when the next clock pulse is received at the CK input the flip-flops will toggle, following their normal sequence.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

 

Asynchronous Parallel Load    

While common Synchronous Counters Electrical Engineering (EE) Notes | EduRev inputs can produce outputs of 0000 or 1111, a PARALLEL LOAD Synchronous Counters Electrical Engineering (EE) Notes | EduRev input will allow any value to be loaded into the counter. Using a separate DATA input for each flip-flop, and a small amount of extra logic, a logic 0 on the Synchronous Counters Electrical Engineering (EE) Notes | EduRev will load the counter with any pre-determined binary value before the start of, or during the count. A method of achieving asynchronous parallel loading on a synchronous counter is shown in Fig. 5.6.14.

 

Synchronous Counters Electrical Engineering (EE) Notes | EduRev 

 

 

Load Operation

The binary value to be loaded into the counter is applied to inputs D0 to D3 and a logic 0 pulse is applied to the Synchronous Counters Electrical Engineering (EE) Notes | EduRev input. This logic 0 is inverted and applied to one input of each of the eight NAND gates to enable them. If the value to be loaded into a particular flip-flop is logic 1, this makes the inputs of the right hand NAND gate 1,1 and due to the inverter between the pair of NAND gates for that particular input, the left hand NAND gate inputs will be 1,0.

The result of this is that logic 0 is applied to the flip-flop Synchronous Counters Electrical Engineering (EE) Notes | EduRev input and logic 1 is applied to the Synchronous Counters Electrical Engineering (EE) Notes | EduRev input. This combination sets the Q output to logic 1, the same value that was applied to the D input. Similarly if a D input is at logic 0 the output of the left hand NAND gate of the pair will be Logic 0 and the right hand gate output will be logic 1, which will clear the Q output of the flip-flop. Because the Synchronous Counters Electrical Engineering (EE) Notes | EduRev input is common to each pair of load NAND gates, all four flip-flops are loaded simultaneously with the value, either 1 or 0 present at its particular D input.

 

Multiple Inputs and Outputs

Modifications such as those described in this module make the basic synchronous counter much more versatile. Both TTL and CMOS synchronous counters are available in the 74 series of ICs containing usually 4-bit counters with these and other modifications for a wide variety of applications. Fig 5.6.15 shows how all the input functions described above, plus some important outputs such as Ripple Carry (RC) and Terminal Count (TC) can be combined to form a single synchronous counter IC.

A typical single synchronous IC such as the 74HC191 four-bit binary up/down counter also uses these input and output functions, which are designated on NXP versions (Fig. 5.6.16) as follows:

 

Inputs  

• D0, D1, D2 and D3 (Load inputs) - A 4 bit binary number may be loaded into the counter via these inputs when the Parallel Load input PL is at logic 0.

• Synchronous Counters Electrical Engineering (EE) Notes | EduRev (Count Enable) - Allows the count to proceed when at 0. Stops count without resetting when at logic 1.

• Synchronous Counters Electrical Engineering (EE) Notes | EduRev (Up/Down) - Counts up when 0, down when at logic 1.

• CP - Clock Pulse input.

 

Outputs

• Q0, Q1, Q2 and Q3 - Four bit binary output.

• TC (Terminal Count) - Also called MAX/MIN in some versions, gives a logic 1 pulse, equal in width to one full clock cycle, at each change over of the most significant bit (signifying that the count has overflowed beyond the end of an up or down count). TC can be used to detect the end of an up or down count, and as well as being available as an output, TC is used internally to generate the Ripple Carry output.

• Synchronous Counters Electrical Engineering (EE) Notes | EduRev (Ripple Carry) - Outputs a logic 0 pulse, equal in width to the low portion of the clock cycle at the end of a count, and when connected to the clock input of another 74HC191 IC it acts as a ‘carry’ to the next counter.

Synchronous Counters Electrical Engineering (EE) Notes | EduRev

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