Lecture 22 - Design of Digital Control Systems with Dead Beat Response - Electrical Engineering (EE) PDF Download

Clear all your Electrical Engineering (EE) doubts with EduRev Join for Free

Join for Free

Lecture 22 - Design of digital control systems with dead beat response, Control Systems

1 Design of digital control systems with dead beat response

So far we have discussed the design methods which are extensions of continuous time design techniques.

We will now deal with the dead beat response design of digital control system.

We must distinguish between the designs of deadbeat response for a digital control system, where all the components are sub ject to only digital data, and a sampled data control system, where both continuous and discrete components are present.

An all digital control system is shown in Figure 1.

Figure 1: An all digital control system

The transfer function of the digital plant is given by

Let us assume that the transfer function of the cascade digital controller is

Thus the open loop transfer function becomes

And we get the closed loop transfer function as

Thus for unit step input, the output comes out to be

Thus, the output c(k) represents a unit step response where k starts from 1, that is one sample later.

In other words, c(k) reaches the desired steady state value 1, in one sampling period with out any overshoot and stays there for ever.

This type of response is known as dead beat response.

One should note that if G_p(z) was the result of sampling a continuous data system, the D_c(z) does not guarantee that no ripples occur between two sampling instants in constant output c(t).
 

1.1 Deadbeat response design when the system poles and zeros are inside the unit circle Design criteria:

1. The system must have a zero steady state error at sampling instants.

2. The time to reach final output must be finite and minimum.

3. The controller should be physically realizable, i.e., it should be causal.

We can write from Figure 1,

Thus

The error signal

E (z) = R(z) − C (z) = 

Let us assume

where, N : positive integer A(z): polynomial in z⁻¹ with no zeros at z = 1.

For unit step signal A(z) = 1 and N = 1.

For unit ramp signal A(z) = T z⁻¹ and N = 2.

To achieve zero steady state error

Since A(z ) does not contain any zero at z = 1, necessary condition for zero steady state error is that 1 − M (z ) should contain (1 − z ⁻¹)N as a factor, i.e.,

1 − M (z) = (1 − z⁻¹)^N F (z)

or,

where, F (z ) is a polynomial in z ⁻¹.

Q(z ) is a polynomial in z .

Substituting M (z) in the expression of E (z), E (z) = A(z)F (z). Since A(z) and F (z) are both polynomials of z⁻¹, E (z) will have a finite number of terms in the power series in the inverse power of z , i.e., the error will go to zero in a finite number of sampling periods.

Physical realizability of D_c(z) : Physical realizability condition on D_c(z ) imposes constraints on the form of M (z ). Let

where, n and k are the excess poles over zeros of G_p(z ) and M (z ) respectively. This implies

For D_c(z ) to be realizable, k ≥ n, i.e., excess of poles over zeros for M (z ) must be at least equal to excess of poles over zeros for G_p(z ).

Thus, if G_p(z ) does not have poles or zeros outside the unit circle, then M (z ) should have the following forms.

1. Step input :

2. Ramp input:

Try to prove the above as an exercise problem.

Example 1: Let us consider the earlier example where

When the input is a step function, M (z) = z⁻¹

Thus

Figure 2: Deadbeat response of an all digital control system for unit step input

Hence the output sequence follows the input after one sampling instant. Figure 2 shows the output response.

When the input is a ramp function

Thus

We can conclude from the above expression that the output sequence follows the input after 2 sampling periods which is shown in Figure 3.

Figure 3: Deadbeat response of an all digital control system for unit ramp input
 

Example 2:

When the input is a step function, M (z) = z⁻²

Thus

Hence the output sequence follows the input after two sampling instants.