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Physics Exam  >  Physics Notes  >  Physics for IIT JAM, UGC - NET, CSIR NET  >  Digital Counters - Digital Electronics, CSIR-NET Physical Sciences

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET PDF Download

Counter is a sequential circuit. A digital circuit which is used for a counting pulses is known counter. Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied. Counters are of two types.

  • Asynchronous or ripple counters.

  • Synchronous counters.

 

Asynchronous or ripple counters

The logic diagram of a 2-bit ripple up counter is shown in figure. The toggle (T) flip-flop are being used. But we can use the JK flip-flop also with J and K connected permanently to logic 1. External clock is applied to the clock input of flip-flop A and QA output is applied to the clock input of the next flip-flop i.e. FF-B.

Logical Diagram

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET

Operation

S.N.

Condition

Operation

1

Initially let both the FFs be in the reset state

QBQA = 00 initially

2

After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will be equal to 1.

QA is connected to clock input of FF-B. Since QA has changed from 0 to 1, it is treated as the positive clock edge by FF-B. There is no change in QB because FF-B is a negative edge triggered FF.

QBQA = 01 after the first clock pulse.

3

After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA = 0.

The change in QA acts as a negative clock edge for FF-B. So it will also toggle, and QBwill be 1.

QBQA = 10 after the second clock pulse.

4

After 3rd negative clock edge

On the arrival of 3rd negative clock edge, FF-A toggles again and QA become 1 from 0.

Since this is a positive going change, FF-B does not respond to it and remains inactive. So QB does not change and continues to be equal to 1.

QBQA = 11 after the third clock pulse.

5

After 4th negative clock edge

On the arrival of 4th negative clock edge, FF-A toggles again and QA becomes 1 from 0.

This negative change in QAacts as clock pulse for FF-B. Hence it toggles to change QBfrom 1 to 0.

QBQA = 00 after the fourth clock pulse.

Truth Table

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET


Synchronous counters

If the "clock" pulses are applied to all the flip-flops in a counter simultaneously, then such a counter is called as synchronous counter.

2-bit Synchronous up counter

The JA and KA inputs of FF-A are tied to logic 1. So FF-A will work as a toggle flip-flop. The JB and KB inputs are connected to QA.

 

Logical Diagram

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET

Operation

S.N.

Condition

Operation

1

Initially let both the FFs be in the reset state

QBQA = 00 initially.

2

After 1st negative clock edge

As soon as the first negative clock edge is applied, FF-A will toggle and QA will change from 0 to 1.

But at the instant of application of negative clock edge, QA , JB = KB = 0. Hence FF-B will not change its state. So QB will remain 0.

QBQA = 01 after the first clock pulse.

3

After 2nd negative clock edge

On the arrival of second negative clock edge, FF-A toggles again and QA changes from 1 to 0.

But at this instant QA was 1. So JB = KB= 1 and FF-B will toggle. Hence QB changes from 0 to 1.

QBQA = 10 after the second clock pulse.

4

After 3rd negative clock edge

On application of the third falling clock edge, FF-A will toggle from 0 to 1 but there is no change of state for FF-B.

QBQA = 11 after the third clock pulse.

5

After 4th negative clock edge

On application of the next clock pulse, QA will change from 1 to 0 as QB will also change from 1 to 0.

QBQA = 00 after the fourth clock pulse.


Classification of counters

Depending on the way in which the counting progresses, the synchronous or asynchronous counters are classified as follows −

  • Up counters

  • Down counters

  • Up/Down counters

 

UP/DOWN Counter

Up counter and down counter is combined together to obtain an UP/DOWN counter. A mode control (M) input is also provided to select either up or down mode. A combinational circuit is required to be designed and used between each pair of flip-flop in order to achieve the up/down operation.

  • Type of up/down counters

  • UP/DOWN ripple counters

  • UP/DOWN synchronous counter

 

UP/DOWN Ripple Counters

In the UP/DOWN ripple counter all the FFs operate in the toggle mode. So either T flip-flops or JK flip-flops are to be used. The LSB flip-flop receives clock directly. But the clock to every other FF is obtained from (Q = Q bar) output of the previous FF.

  • UP counting mode (M=0) − The Q output of the preceding FF is connected to the clock of the next stage if up counting is to be achieved. For this mode, the mode select input M is at logic 0 (M=0).

  • DOWN counting mode (M=1) − If M = 1, then the Q bar output of the preceding FF is connected to the next FF. This will operate the counter in the counting mode.

Example

3-bit binary up/down ripple counter.

  • 3-bit − hence three FFs are required.

  • UP/DOWN − So a mode control input is essential.

  • For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one.

  • For a ripple up counter, the Q output of preceding FF is connected to the clock input of the next one.

  • For a ripple down counter, the Q bar output of preceding FF is connected to the clock input of the next one.

  • Let the selection of Q and Q bar output of the preceding FF be controlled by the mode control input M such that, If M = 0, UP counting. So connect Q to CLK. If M = 1, DOWN counting. So connect Q bar to CLK.

Block Diagram

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET

Truth Table

Digital Counters - Digital Electronics, CSIR-NET Physical Sciences | Physics for IIT JAM, UGC - NET, CSIR NET

Operation

S.N.

Condition

Operation

1

Case 1 − With M = 0 (Up counting mode)

If M = 0 and M bar = 1, then the AND gates 1 and 3 in fig. will be enabled whereas the AND gates 2 and 4 will be disabled.

Hence QA gets connected to the clock input of FF-B and QBgets connected to the clock input of FF-C.

These connections are same as those for the normal up counter. Thus with M = 0 the circuit work as an up counter.

2

Case 2: With M = 1 (Down counting mode)

If M = 1, then AND gates 2 and 4 in fig. are enabled whereas the AND gates 1 and 3 are disabled.

Hence QA bar gets connected to the clock input of FF-B and QB bar gets connected to the clock input of FF-C.

These connections will produce a down counter. Thus with M = 1 the circuit works as a down counter.

 

Modulus Counter (MOD-N Counter)

The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8 counter. So in general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2n.

Type of modulus

  • 2-bit up or down (MOD-4)

  • 3-bit up or down (MOD-8)

  • 4-bit up or down (MOD-16)

 

Application of counters

  • Frequency counters

  • Digital clock

  • Time measurement

  • A to D converter

  • Frequency divider circuits

  • Digital triangular wave generator.

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FAQs on Digital Counters - Digital Electronics, CSIR-NET Physical Sciences - Physics for IIT JAM, UGC - NET, CSIR NET

1. What is a digital counter in digital electronics?
Ans. A digital counter is an electronic device or circuit that counts the number of events or pulses occurring in a digital signal. It can be used to track the number of occurrences of a particular event or to measure time intervals. Digital counters are widely used in various applications such as digital clocks, frequency dividers, and event counters.
2. How does a digital counter work?
Ans. A digital counter consists of flip-flops, logic gates, and combinational circuits. The basic working principle involves using flip-flops to store and propagate the count. Each flip-flop represents a binary bit (0 or 1) of the count. When an input pulse or event occurs, the flip-flops change their states according to the logic design of the counter. This change in states creates a sequence of counts, allowing the counter to increment or decrement based on the input signals.
3. What are the different types of digital counters?
Ans. There are several types of digital counters, including ripple counters, synchronous counters, up counters, down counters, and ring counters. - Ripple counters: In a ripple counter, the output of one flip-flop serves as the clock input for the next flip-flop. This sequential connection allows the counter to count in a ripple fashion. - Synchronous counters: Synchronous counters use a common clock signal for all the flip-flops, allowing them to change states simultaneously. This eliminates the ripple effect and provides faster counting. - Up counters: Up counters increment the count by one for each input pulse or event. They count upwards in binary representation. - Down counters: Down counters decrement the count by one for each input pulse or event. They count downwards in binary representation. - Ring counters: Ring counters are circular shift registers, where the output of one flip-flop is connected to the input of the next flip-flop. The count circulates in a ring fashion.
4. How can digital counters be used in digital electronics?
Ans. Digital counters have various applications in digital electronics. Some common uses include: - Digital clocks: Digital counters can be used to display and track time in digital clocks. Each digit of the clock is controlled by a separate counter that counts from 0 to 9. - Frequency dividers: Digital counters can divide the frequency of an input signal by a specific factor. This is useful in various applications, such as generating clock signals with different frequencies. - Event counters: Digital counters can count the number of occurrences of a specific event. This is helpful in applications where the number of events needs to be tracked or measured. - Traffic light control: Digital counters can be utilized in traffic light control systems to manage the timing and sequencing of traffic lights.
5. What are the advantages of digital counters?
Ans. Digital counters offer several advantages, including: - Accuracy: Digital counters provide precise counting and are not susceptible to errors due to noise or signal degradation. - Flexibility: Digital counters can be easily programmed or configured to count in different ways, such as up counting, down counting, or even skipping numbers. - Scalability: Digital counters can be cascaded or combined to create larger counters with higher counting capabilities. - Speed: Digital counters can count at high speeds, making them suitable for applications that require fast counting or timing. - Integration: Digital counters can be integrated with other digital circuits or systems, allowing for seamless functionality and control.
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