Add & Subtract using 2's Complement - Digital Circuits - Electronics and Communication

Introduction

In binary arithmetic, 2's complement is the most common method for representing signed integers and performing addition and subtraction. Its advantages over 1's complement include a single representation for zero and simpler arithmetic (no end-around carry adjustment). In this chapter we explain how to add and subtract binary numbers using 2's complement, show the possible cases, give worked examples (using consistent fixed register widths), and state the rule for detecting overflow.

Addition using 2's complement

Procedure to add two signed binary numbers in 2's complement form (register width must be chosen and both operands sign-extended to that width):

• Ensure both operands are represented with the same number of bits (sign-extend if necessary).
• Add the two binary numbers, bit by bit, producing any carry out beyond the most significant bit (MSB).
• Discard the final carry out (carry beyond MSB). The remaining bits are the raw result.
• Check for overflow: if the two operands have the same sign and the result has the opposite sign, an overflow has occurred and the result is not a correct representation in the chosen bit width.

Case 1: Positive + Negative where positive magnitude is larger

When a positive number and a negative number are added and the positive magnitude is larger, the final result is positive. Add the two representations; any carry out is discarded; interpret remaining bits as a positive 2's complement number.

Example (using 5-bit registers): 1101 and -1001

We express the 4-bit patterns given as 5-bit by sign-extending the positive numbers to 5 bits for consistent arithmetic: 1101 → 01101; 1001 → 01001. We perform +13 and -9 in 5 bits.

01101 ( +13 )
two's complement of 01001 ( +9 ) gives 10111 ( -9 )
01101 + 10111 = 1 00100
Discard the carry out (leftmost 1).
Result = 00100 = +4.
Interpretation: +13 + (-9) = +4 (no overflow).

Case 2: Positive + Negative where negative magnitude is larger

When a positive and a negative number are added and the negative magnitude is larger, the result is negative. After addition, there will be no final carry out; take the 2's complement of the raw result to obtain the magnitude, and attach a negative sign.

Example (using 5-bit registers): 1101 and -1110

We use 01101 for +13 and 01110 for +14, then form -14 by two's complement.

01101 ( +13 )
two's complement of 01110 ( +14 ) gives 10010 ( -14 )
01101 + 10010 = 11111 (no carry out)
Take two's complement of 11111: invert → 00000, add 1 → 00001
Result = -00001 = -1.
Interpretation: +13 + (-14) = -1 (no overflow).

Case 3: Negative + Negative

When two negative numbers are added the algebraic result is negative. In fixed-width 2's complement arithmetic:

• Add the two negative operands (their 2's complement representations).
• Discard any final carry out.
• If the raw result has a 1 in the sign bit, the result is negative and its magnitude is the 2's complement of the raw result (unless overflow occurred).
• If two negative operands produce a positive raw result, an overflow has occurred and the true mathematical sum cannot be represented in the chosen register width.

Example (five-bit register): -1101 and -1110

Represent +1101 and +1110 as 5-bit positives then form their two's complements to obtain the negative operands.

01101 ( +13 ) → two's complement → 10011 ( -13 )
01110 ( +14 ) → two's complement → 10010 ( -14 )
10011 + 10010 = 1 00101
Discard the carry out (leftmost 1).
Raw result = 00101 ( +5 )
Both operands were negative but raw result is positive → overflow has occurred in 5 bits.
Interpretation: mathematically -13 + (-14) = -27, which is not representable in 5 bits (wraps to +5); therefore the computed 00101 is not a correct signed result in 5-bit arithmetic (overflow).

Overflow rule (summary for addition)

• If the two operands have different signs, overflow cannot occur (result magnitude lies between operands).
• If the two operands have the same sign and the result has a different sign, overflow has occurred.
• In hardware, overflow can be detected by examining the carry into the MSB and the carry out of the MSB: if they differ, overflow has occurred.

Subtraction using 2's complement

Subtraction A - B can be implemented as A + (-B). Using 2's complement, convert the subtrahend B into its 2's complement (i.e., form -B) and add it to A. The same overflow rules for addition apply.

• Form the 2's complement of the subtrahend (invert all bits, then add 1).
• Add that complement to the minuend.
• If there is a carry out beyond MSB, discard it and the result is positive. If there is no carry out, the result is negative; take the 2's complement of the raw result to obtain the magnitude and attach the negative sign. Always check overflow when operands sign conditions indicate it.

Example 1: 10101 - 00111

Use 5-bit arithmetic as given.

Subtrahend = 00111.
Two's complement of subtrahend: invert 11000, add 1 → 11001.
Minuend = 10101.
Add: 10101 + 11001 = 1 01110.
Discard the carry out.
Result = 01110 = +14.
Interpretation: 21 - 7 = 14 (positive result, no overflow).

Example 2: 10101 - 10111

Use 5-bit arithmetic as given.

Subtrahend = 10111.
Two's complement of subtrahend: invert 01000, add 1 → 01001.
Minuend = 10101.
Add: 10101 + 01001 = 11110 (no carry out).
No carry out → result is negative. Take two's complement of 11110: invert 00001, add 1 → 00010.
Result = -00010 = -2.
Interpretation: 21 - 23 = -2 (correct, no overflow).

Practical notes and applications

• Register width matters: choose a register size that accommodates the expected range of values; otherwise arithmetic can overflow and wrap around.
• Hardware use: 2's complement arithmetic is widely used in processors and digital circuits because addition and subtraction share the same adder hardware and zero has a single representation.
• Overflow detection: use sign-bit checks or the MSB carry-in vs carry-out method in digital designs.
• Sign extension: when increasing bit width, replicate the sign bit into the new upper bits (sign extension) to preserve the numeric value.

Summary

To add or subtract signed binary numbers in 2's complement: align bit widths, use two's complement for negative operands, add using a binary adder, discard the final carry out, and check for overflow when operands share the same sign. Practising with fixed register widths and checking the sign bits after addition helps avoid mistakes and ensures correct interpretation of results.