Data Selectors & Multiplexers - Analog and Digital Electronics - Electrical

Introduction

In digital electronics, selection between several data sources is normally implemented by combinational logic circuits. Logic signals applied to one or more select inputs determine which data input is routed to the output. The selected data may be a single logic level or a stream of digital information. Switching by logic gates is faster and more reliable than mechanical contacts, and so digital data selectors and multiplexers are fundamental building blocks in many systems.

The terms data selector and multiplexer are often used interchangeably. When a circuit chooses between two inputs it is commonly called a data selector; when it combines many inputs into one output it is commonly called a multiplexer (or MUX). Multiplexers exist in both digital and analogue forms and are used wherever many signals must share a single transmission path or processing channel.

Basic Data Select (Multiplexer) Circuits

A simple data selector consisting of a single XOR gate was used in the 8-bit adder/subtractor circuit shown in Figs. 4.1.5 and 4.1.6 in Module 4.1 to change the function of the circuit from addition to subtraction. In that application the XOR gate was used to select either data B or its inverse B̄ so that addition with two's complement subtraction could be performed. For selection between two independent data inputs a small combinational circuit is required.

A common and instructive implementation of a 2-to-1 digital multiplexer uses three NAND gates. The arrangement enables one of two data inputs to reach the output, but not both simultaneously. Two NAND gates form input gating stages; a third NAND gate combines their outputs to produce the final selected output.

The operation of the NAND-based selector is straightforward and relies on enabling or disabling each gate by using the select signal and its complement. Consider a NAND gate with inputs X and Y. From the NAND truth table, if one input (say X) is held at logic 1 the gate behaves as an inverter for the other input; the gate is said to be enabled. If X is held at logic 0 the NAND output is always logic 1 regardless of Y; the gate is then disabled and the second input cannot influence the output. Using a pair of such enabled/disabled gates and a final combining NAND produces a conventional 2:1 multiplexer.

Apply this behaviour to the two input gating NANDs: when the select input making A gate enabled is at logic 1, that NAND produces the inverted form of the A data; when the select input making the gate disabled is at logic 0 the gate output is fixed at logic 1 and A cannot propagate. The other gate behaves similarly for input B. The final NAND combines the two gated outputs so that the correct (non-inverted) selected data appears at the multiplexer output. Table 4.2.2 summarises the selection function for a 2:1 multiplexer.

The canonical Boolean expression for a 2:1 multiplexer is

Y = S̄·A + S·B

Using NAND gates the same function is realised without explicit AND/OR blocks by forming the terms A·S̄ and B·S with NAND gates and then NANDing their outputs; the double negation from NAND logic restores the required OR operation. The design method is useful when NAND gates are the preferred or only available building blocks.

Multiplexer sizes and select lines

• A multiplexer that selects one of n inputs is called an n:1 multiplexer; common sizes are 2:1, 4:1, 8:1 and 16:1.
• The number of select lines required is ⌈log2 n⌉; for example, an 8:1 MUX needs 3 select lines because 23 = 8.
• Multiplexers can be cascaded to form larger selectors: two 4:1 MUXs feeding a 2:1 MUX can implement an 8:1 selector.

Analogue multiplexers and sample switching

Analogue multiplexers connect one of several analogue voltage signals to a single output under control of digital select lines. They are constructed using transistor switches or specialised CMOS transmission gates. When an analogue MUX is used to sample a selected channel and the signal must be held while another channel is selected, a sample-and-hold stage is often used after the MUX to preserve the value until it is processed.

Demultiplexers and the inverse function

A demultiplexer performs the inverse operation of a multiplexer: a single input is routed to one of many outputs, under control of select lines. Demultiplexers are used where a single data source must be delivered to one of several destinations in time-division systems.

Applications

• Time-division multiplexing of digital signals for serial transmission and bus sharing.
• Selecting inputs for analogue-to-digital converters (ADC) in data-acquisition systems.
• Routing data paths in arithmetic logic units, register files and control logic inside processors.
• Signal routing in test equipment, instrumentation and measurement systems.
• Multiplexed displays and keyboard encoders/decoders in user interfaces.

Design considerations and practical notes

• Propagation delay: each gate in the MUX path adds delay. For high-speed systems estimate the worst-case path delay and ensure timing requirements are met.
• Fan-out and loading: drive capability of select lines and outputs must be sufficient for the loads connected; buffering or tri-state drivers may be needed.
• Glitches: when select lines change, brief hazards or glitches can occur at the output if input changes are not synchronous; synchronous selection or added gating can reduce unwanted pulses.
• Power consumption: CMOS MUX ICs are low power in steady state but switching frequency increases dynamic power dissipation.
• Analogue bandwidth and on-resistance: for analogue MUXs, the on-resistance of switches and channel capacitance limit frequency response.

Summary

Multiplexers (data selectors) are compact combinational circuits that route one of many inputs to a single output under the control of select signals. They replace mechanical switches in electronic systems for faster, more reliable selection. Basic implementations include the 2:1 MUX realised with three NAND gates and larger MUXs created by cascading. Analogue and digital MUXs serve in many applications from data acquisition to processor datapaths; practical design must consider delay, loading, glitches and, for analogue devices, bandwidth.