Switch De-Bouncing: S-R Flip Flops | Analog and Digital Electronics - Electrical Engineering (EE) PDF Download

Switch De-Bouncing

The repeated pulses at the inputs are ignored after the initial pulse has set or reset the Q output, which makes the SR flip-flop useful for switch de-bouncing.

When any moving object collides with a stationary object it tends to bounce; the contacts in mechanical switches are no exception. Although the contacts and the movement may be small, as the contacts close they will tend to make and break contact several times in very rapid succession rather than close and remain closed. This effect is called switch bounce or contact bounce.

The bounce causes a number of very fast on and off states for a short interval until the contacts settle in the closed position. The length of time of the bouncing is often short (typically a few milliseconds), but in digital circuits the rapid ones and zeros produced during bounce are interpreted as additional switch actuations and can cause incorrect counting, multiple triggers or spurious logic events.

For example, a timing waveform such as the one shown in Fig. 5.2.3 may display a number of fast pulses for about 2 ms after the switch is initially closed (indicated by a marker such as a red arrow). In many low-speed or analogue applications this brief disturbance may be neglected, but in digital systems any bounce that occurs while the circuit samples the switch can produce erroneous behaviour.

Switch De-Bounce Circuit Using an SR Flip-Flop

An effective and widely used method to remove the effects of switch bounce is to use an SR flip-flop (or SR latch implemented with NAND gates) to convert the noisy switch transitions into a single clean change of the output. The circuit arrangement and timing are illustrated in Fig. 5.2.4.

The circuit uses a changeover switch labelled SW1 which is a break-before-make (B-B-M) type. Resistor R1 is used to pull the appropriate input to logic 1 when the switch is not connecting that input to 0 V. When SW1 connects the upper contact to 0 V, the S input changes from logic 1 to logic 0 while R is held at logic 1 by R1. As soon as the input shown by

is at logic 0 (at time 'a' in Fig. 5.2.4), the output Q becomes logic 1 and any subsequent rapid pulses caused by switch bounce are ignored because the flip-flop remains in the set condition.

When SW1 is moved to the lower contact there is a short interval (between times labelled 'b' and 'c' in Fig. 5.2.4) during which neither

nor

is connected to 0 V. During that interval,

returns to logic 1, so both inputs of the SR device are at logic 1 until time 'c'. At time 'c' SW1 connects the R input to 0 V and Q is reset to logic 0, completing a single clean output pulse.

The use of a break-before-make switch rather than a make-before-break switch is important. With B-B-M the changeover period (time 'b' to time 'c') ensures that both inputs go to logic 1 rather than both becoming logic 0. The latter condition would be a non-allowed state (for the SR device used here) where both inputs are logic 0; that state can produce indeterminate outputs. Using B-B-M therefore ensures the outputs Q and

are never forced to the same logic level by the switch action alone.

Although during the changeover both inputs are at logic 1, this does not produce the indeterminate condition noted in Table 5.2.1, because one or other input is always at logic 0 before both inputs become logic 1. In other words, the sequence of input changes prevents the forbidden condition from occurring.

Summary of Operation

• Initial actuation: When the switch first connects S (or R) to 0 V, that input goes low and the corresponding flip-flop output is set (or reset) producing a single change at Q.
• Bounce immunity: Any fast make-break transitions that follow while the input remains asserted are ignored because the flip-flop output remains latched.
• Changeover period: During transfer of the switch between contacts, a break-before-make switch ensures both inputs go to the inactive logic level (logic 1 in this arrangement) rather than both being driven low, avoiding the forbidden input combination.
• Clean pulse generation: The result is a single clean output transition (or pulse) corresponding to one physical switch action, suitable for use by counters, edge detectors or other digital logic.

Practical notes and alternatives

• Typical bounce duration: A few hundred microseconds to several milliseconds depending on switch type and mechanical wear.
• Choice of SR implementation: SR latches may be implemented with NAND or NOR gates; note which input polarities are active and which input combination is forbidden for the chosen implementation.
• Timing diagrams: Always consult the timing diagram (for example Fig. 5.2.4) to verify the relationship between switch movement and output pulses.
• Other methods: Debouncing can also be achieved with RC filters and Schmitt triggers for simple cases, or using monostable multivibrators or microcontroller firmware for programmable behaviour. The SR flip-flop method is simple, reliable and fully hardware based.

Using an SR flip-flop for debouncing provides a robust hardware solution that converts the noisy mechanical contact behaviour into a single deterministic logic transition suitable for digital systems.