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Test: Differential Amplifiers - Electronics and Communication Engineering (ECE) MCQ


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10 Questions MCQ Test - Test: Differential Amplifiers

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Test: Differential Amplifiers - Question 1

A resitive loaded and biased differential amplifier circuit is shown in figure. Neglecting the base currents and assuming matched transistors with VA = ∞,β = 100, w hat are the values of Rc and RE to meet the following specifications?
Differential mode gain (double ended) = -500,
Common mode rejection ratio = 500,
Differential mode input resistance = 2 MQ. 

Detailed Solution for Test: Differential Amplifiers - Question 1

Test: Differential Amplifiers - Question 2

In the level shifter circuit shown in figure beiow, the internal drop across each diode VD = VBE2 = 0.7 V and hfe is very large.
The value of R for V0 to become zero is

Detailed Solution for Test: Differential Amplifiers - Question 2

The aiven circuit is redrawn as shown below.

Writing loop equation containing two diodes and

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Test: Differential Amplifiers - Question 3

A differential amplifier, amplifies

Detailed Solution for Test: Differential Amplifiers - Question 3

The goal of designing differential amplifiers is to minimize the effect of common-mode input signal and amplify the difference of the voltages between the two input lines.

Test: Differential Amplifiers - Question 4

Most of linear ICs are based on the two transistor differential amplifier because of its

Test: Differential Amplifiers - Question 5

A CE amplifier has RL = 10 KΩ. Given that hie = 1 KΩ, hfe = 50, hre = 0 and 1/hoe = 40 KΩ. Calculate the voltage gain.

Detailed Solution for Test: Differential Amplifiers - Question 5



The net output resistance is: RL’ = 40k ||10k = 8 k

Output voltage : - 50ib.(8k)

Input voltage : ib.(1k)

Test: Differential Amplifiers - Question 6

 In a single-stage differential amplifier, the output offset voltage is basically dependent on the mismatch of

Detailed Solution for Test: Differential Amplifiers - Question 6

In single stage differential amplifier, the output offset voltage is basically dependent on the mismatch of IB and β.

Test: Differential Amplifiers - Question 7

Assertion (A): It is not so easy to design d.c. amplifiers using transistors.
Reason (R): The values of hfe ,VBE and ICBO vary with temperature.

Detailed Solution for Test: Differential Amplifiers - Question 7

The values of hFE, VBE and ICB0 vary with temperature and due to the variation in any of these quantities the output voltage may change which may not be distinguished from a change in the input signal voltage, Due to this reason it is not so easy to design d.c. amplifiers using transistors. Hence, both assertion and reason are true and reason is the correct explanation of assertion.

Test: Differential Amplifiers - Question 8

Assertion (A): The ability of a differential amplifier to reject a differential mode signal is called its “figure of merit”.
Reason (R): The ideal value of figure of merit of a differential amplifier is infinite.

Detailed Solution for Test: Differential Amplifiers - Question 8

Assertion is not true because “figure of merit” (or CM MR) of a differential amplifier is to reject a common mode signal (vC).

Test: Differential Amplifiers - Question 9

A differential amplifier has (i) CMMR= 1000 and (ii) CMRR= 10000.
The first set of inputs is V1= 100 μV and V2, = -100μV.
The second set of inputs is V1= 1100 μV and V2 = 900 μV.
What is the percentage difference in output voltage obtained for the two sets of input voltages?

Detailed Solution for Test: Differential Amplifiers - Question 9

we know that

Now,

From equation (iii) and (iv), the percentage difference in output voltage obtained for the two sets of input voltages

Test: Differential Amplifiers - Question 10

The Q-point (Vc and IB) for the differential amplifier shown in figure below is given by:

Detailed Solution for Test: Differential Amplifiers - Question 10

Also

Hence, both transistors of the differential amplifier are biased at a Q-point having lB = 1.09 μA and Vc=7.9V.

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