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Test: Memory Management- 2 - Computer Science Engineering (CSE) MCQ


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20 Questions MCQ Test - Test: Memory Management- 2

Test: Memory Management- 2 for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: Memory Management- 2 questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Memory Management- 2 MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Memory Management- 2 below.
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Test: Memory Management- 2 - Question 1

The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by

Detailed Solution for Test: Memory Management- 2 - Question 1

There are two important tasks in virtual memory management: a page-replacement strategy and a frame-allocation strategy. Frame allocation strategy says gives the idea of minimum number of frames which should be allocated. The absolute minimum number of frames that a process must be allocated is dependent on system architecture, and corresponds to the number of pages that could be touched by a single (machine) instruction. So, it is instruction set architecture i.e. option (A) is correct answer.

Test: Memory Management- 2 - Question 2

Consider a system with a two-level paging scheme in which a regular memory access takes 150 nanoseconds, and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and two memory accesses. The TLB hit ratio is 90%, and the page fault rate is one in every 10,000 instructions. What is the effective average instruction execution time?

Detailed Solution for Test: Memory Management- 2 - Question 2

Please note that page fault rate is given one page fault per 10,000 instructions. Since there are two memory accesses per instruction, so we need double address translation time for average instruction execution time. Also, there are 2 page table accessed if TLB miss occurred. TLB access assumed as 0. Therefore, Average Instruction execution time = Average CPU execution time + Average time for getting data(instruction operands from memory for each instruction) = Average CPU execution time + Average address translation time for each instruction + Average memory fetch time for each instruction + Average page fault time for each instruction = 100 + 2×(0.9×(0)+0.1×(2×150)) + 2×150 + 1 /10000 × 8 × 106 = 100 + 60 + 300 + 800 = 1260 ns So, none option is correct.

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Test: Memory Management- 2 - Question 3

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns)

Detailed Solution for Test: Memory Management- 2 - Question 3

The possibilities are
 TLB Hit*Cache Hit +
 TLB Hit*Cache Miss + 
 TLB Miss*Cache Hit +
 TLB Miss*Cache Miss
= 0.96*0.9*2 + 0.96*0.1*12 + 0.04*0.9*22 + 0,04*0.1*32
= 3.8
≈ 4 
Why 22 and 32? 22 is because when TLB miss occurs it takes 1ns and the for the physical address it has to go through two level page tables which are in main memory and takes 2 memory access and the that page is found in cache taking 1 ns which gives a total of 22

Test: Memory Management- 2 - Question 4

Which of the following is not a form of memory?

Detailed Solution for Test: Memory Management- 2 - Question 4

Instruction Cache - Used for storing instructions that are frequently used Instruction Register - Part of CPU's control unit that stores the instruction currently being executed Instruction Opcode - It is the portion of a machine language instruction that specifies the operation to be performed Translation Lookaside Buffer - It is a memory cache that stores recent translations of virtual memory to physical addresses for faster access.   So, all the above except Instruction Opcode are memories. Thus, C is the correct choice.   Please comment below if you find anything wrong in the above post.

Test: Memory Management- 2 - Question 5

Dynamic linking can cause security concerns because:

Detailed Solution for Test: Memory Management- 2 - Question 5

Static Linking and Static Libraries is the result of the linker making copy of all used library functions to the executable file. Static Linking creates larger binary files, and need more space on disk and main memory. Examples of static libraries (libraries which are statically linked) are, .a files in Linux and .lib files in Windows. Dynamic linking and Dynamic Libraries Dynamic Linking doesn’t require the code to be copied, it is done by just placing name of the library in the binary file. The actual linking happens when the program is run, when both the binary file and the library are in memory. Examples of Dynamic libraries (libraries which are linked at run-time) are, .so in Linux and .dll in Windows. In Dynamic Linking,the path for searching dynamic libraries is not known till runtime    

Test: Memory Management- 2 - Question 6

The optimal page replacement algorithm will select the page that

Detailed Solution for Test: Memory Management- 2 - Question 6

The optimal page replacement algorithm will select the page whose next occurrence will be after the longest time in future. For example, if we need to swap a page and there are two options from which we can swap, say one would be used after 10s and the other after 5s, then the algorithm will swap out the page that would be required 10s later. Thus, B is the correct choice.   Please comment below if you find anything wrong in the above post.

Test: Memory Management- 2 - Question 7

The process of assigning load addresses to the various parts of the program and adjusting the code and date in the program to reflect the assigned addresses is called

Detailed Solution for Test: Memory Management- 2 - Question 7

Relocation of code is the process done by the linker-loader when a program is copied from external storage into main memory.
A linker relocates the code by searching files and libraries to replace symbolic references of libraries with actual usable addresses in memory before running a program.
Thus, option (C) is the answer.

Test: Memory Management- 2 - Question 8

Where does the swap space reside?

Detailed Solution for Test: Memory Management- 2 - Question 8

Swap space is an area on disk that temporarily holds a process memory image.   When memory is full and process needs memory, inactive  parts of process are put in swap space of disk.
 

Test: Memory Management- 2 - Question 9

A computer system implements a 40 bit virtual address, page size of 8 kilobytes, and a 128-entry translation look-aside buffer (TLB) organized into 32 sets each having four ways. Assume that the TLB tag does not store any process id. The minimum length of the TLB tag in bits is _________

Detailed Solution for Test: Memory Management- 2 - Question 9

Total virtual address size = 40

Since there are 32 sets, set offset = 5

Since page size is 8kilobytes, word offset = 13

Minimum tag size = 40 - 5- 13 = 22

Test: Memory Management- 2 - Question 10

Consider six memory partitions of size 200 KB, 400 KB, 600 KB, 500 KB, 300 KB, and 250 KB, where KB refers to kilobyte. These partitions need to be allotted to four processes of sizes 357 KB, 210 KB, 468 KB and 491 KB in that order. If the best fit algorithm is used, which partitions are NOT allotted to any process?

Detailed Solution for Test: Memory Management- 2 - Question 10

Best fit allocates the smallest block among those that are large enough for the new process. So the memory blocks are allocated in below order.
357 ---> 400
210 ---> 250
468 ---> 500
491 ---> 600
Sot the remaining blocks are of 200 KB and 300 KB

Test: Memory Management- 2 - Question 11

Consider a fully associative cache with 8 cache blocks (numbered 0-7) and the following sequence of memory block requests: 4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7 If LRU replacement policy is used, which cache block will have memory block 7?

Detailed Solution for Test: Memory Management- 2 - Question 11

Block size is =8 Given 4, 3, 25, 8, 19, 6, 25, 8, 16, 35, 45, 22, 8, 3, 16, 25, 7 So from 0 to 7 ,we have
4 3 25 8 19 6 16 35    //25,8 LRU so next 16,35 come in the block.
 45 3 25 8 19 6 16 35
45 22 25 8 19 6 16 35
45 22 25 8 19 6 16 35
45 22 25 8 3 6 16 35     //16 and 25 already there
45 22 25 8 3 7 16 35   //7 in 5th block Therefore , answer is  B

Test: Memory Management- 2 - Question 12

Which one of the following is NOT shared by the threads of the same process?

Detailed Solution for Test: Memory Management- 2 - Question 12

Threads can not share stack (used for maintaining function calls) as they may have their individual function call sequence.os

Test: Memory Management- 2 - Question 13

A disk has 200 tracks (numbered 0 through 199). At a given time, it was servicing the request of reading data from track 120, and at the previous request, service was for track 90. The pending requests (in order of their arrival) are for track numbers. 30 70 115 130 110 80 20 25. How many times will the head change its direction for the disk scheduling policies SSTF(Shortest Seek Time First) and FCFS (First Come Fist Serve)

Detailed Solution for Test: Memory Management- 2 - Question 13

According to Shortest Seek Time First: 90→ 120→ 115-→110→ 130→ 80→ 70→ 30→ 25→ 20 Change of direction(Total 3);  120→15; 110→130; 130→80 According to First Come First Serve: 90→ 120→ 30→ 70→ 115→ 130→ 110→ 80→ 20→ 25 Change of direction(Total 4);  120→30; 30→70; 130→110;20→25 Therefore,Answer is C

Test: Memory Management- 2 - Question 14

Consider a computer system with ten physical page frames. The system is provided with an access sequence a1, a2, ..., a20, a1, a2, ..., a20), where each ai number. The difference in the number of page faults between the last-in-first-out page replacement policy and the optimal page replacement policy is __________ [Note that this question was originally Fill-in-the-Blanks question]

Detailed Solution for Test: Memory Management- 2 - Question 14

LIFO stands for last in, first out a1 to a10 will result in page faults, So 10 page faults from a1 to a10. Then a11 will replace a10(last in is a10), a12 will replace a11 and so on till a20, so 10 page faults from a11 to a20 and a20 will be top of stack and a9…a1 are remained as such. Then a1 to a9 are already there. So 0 page faults from a1 to a9. a10 will replace a20, a11 will replace a10 and so on. So 11 page faults from a10 to a20. So total faults will be 10+10+11 = 31. Optimal a1 to a10 will result in page faults, So 10 page faults from a1 to a10. Then a11 will replace a10 because among a1 to a10, a10 will be used later, a12 will replace a11 and so on. So 10 page faults from a11 to a20 and a20 will be top of stack and a9…a1 are remained as such. Then a1 to a9 are already there. So 0 page faults from a1 to a9. a10 will replace a1 because it will not be used afterwards and so on, a10 to a19 will have 10 page faults. a20 is already there, so no page fault for a20. Total faults 10+10+10 = 30. Difference = 1

Test: Memory Management- 2 - Question 15

In which one of the following page replacement algorithms it is possible for the page fault rate to increase even when the number of allocated frames increases?

Detailed Solution for Test: Memory Management- 2 - Question 15

In some situations FIFO page replacement gives more page faults when increasing the number of page frames. This situation is Belady’s anomaly. Belady’s anomaly proves that it is possible to have more page faults when increasing the number of page frames while using the First in First Out (FIFO) page replacement algorithm. For example, if we consider reference string 3 2 1 0 3 2 4 3 2 1 0 4 and 3 slots, we get 9 total page faults, but if we increase slots to 4, we get 10 page faults

Test: Memory Management- 2 - Question 16

A paging scheme uses a Translation Look-aside Buffer (TLB). A TLB-access takes 10 ns and a main memory access takes 50 ns. What is the effective access time(in ns) if the TLB hit ratio is 90% and there is no page-fault?

Detailed Solution for Test: Memory Management- 2 - Question 16

Effective access time = hit ratio * time during hit + miss ratio * time during miss TLB time = 10ns, Memory time = 50ns Hit Ratio= 90% E.A.T. = (0.90)*(60)+0.10*110 =65

Test: Memory Management- 2 - Question 17

Match the following flag bits used in the context of virtual memory management on the left side with the different purposes on the right side of the table below.

2008_56

Detailed Solution for Test: Memory Management- 2 - Question 17

Dirty:- Dirty bit is used for whenever a page has been modify and we try to replace it and then this has to be written back so it write-back or leave it. Therefore dirty bit is used for write-back policy.

R/W:- R/W is used for page protection. Reference:- It says which page has not referred recently. Hence it is used for page replacement policy.

Valid:- It says wether the page page you are looking for it present in MM or not. If not present in MM then load into the SM i.e. called page intiallisation. Option (d) is correct.

Test: Memory Management- 2 - Question 18

If LRU and Geek page replacement are compared (in terms of page faults) only for above reference string then find the correct statement from the following:

Detailed Solution for Test: Memory Management- 2 - Question 18

mock_59

Test: Memory Management- 2 - Question 19

A multi-user, multi-processing operating system cannot be implemented on hardware that does not support:

a) Address translation

b) DMA for disk transfer

c) At least two modes of CPU execution (privileged and non-privileged).

d) Demand Paging

Detailed Solution for Test: Memory Management- 2 - Question 19

The correct answer would be (a) and (c) as address translation is required in the multi-programming so that no process can go into any other process’s memory. And atleast 2 modes should be present in the CPU execution so that the privileged mode could control the resource allocation of the unprivileged mode users. The DMA and Demand Paging improves the performance of the OS. Hence they are not necessary conditions in a multi-programming. But since (a) and (c) is not answers mentions in the options so the next best option will be (C) containing both (a) and (c) along with (b). So, option (C) is correct.

Test: Memory Management- 2 - Question 20

The overlay tree for a program is as shown below:

hier

What will be the size of the partition (in physical memory) required to load (and run)  this program? 

Detailed Solution for Test: Memory Management- 2 - Question 20

Depth First Traversal from left to right. when we visit a node for first time, it is loaded in main memory and when we visit it for last time, it is pulled out. For the above program, maximum memory will be required when running code portion present at leaves. For D = 2+4+6 = 12 For E = 2+4+8 = 14 For F = 2+6+2 = 10 For G = 2+8+4 = 14 Max(12, 14, 10, 14) = 14

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