Electrical Engineering (EE) Exam  >  Electrical Engineering (EE) Tests  >  Test: Asynchronous Counter - 1 - Electrical Engineering (EE) MCQ

Test: Asynchronous Counter - 1 - Electrical Engineering (EE) MCQ


Test Description

10 Questions MCQ Test - Test: Asynchronous Counter - 1

Test: Asynchronous Counter - 1 for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: Asynchronous Counter - 1 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Asynchronous Counter - 1 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Asynchronous Counter - 1 below.
Solutions of Test: Asynchronous Counter - 1 questions in English are available as part of our course for Electrical Engineering (EE) & Test: Asynchronous Counter - 1 solutions in Hindi for Electrical Engineering (EE) course. Download more important topics, notes, lectures and mock test series for Electrical Engineering (EE) Exam by signing up for free. Attempt Test: Asynchronous Counter - 1 | 10 questions in 20 minutes | Mock test for Electrical Engineering (EE) preparation | Free important questions MCQ to study for Electrical Engineering (EE) Exam | Download free PDF with solutions
*Answer can only contain numeric values
Test: Asynchronous Counter - 1 - Question 1

The maximum clock frequency in MHz of a 4-stage ripple counter, utilizing flip-flops, with each flip-flop having a propagation delay of 20 ns, is ___________. (round off to one decimal place) 


Detailed Solution for Test: Asynchronous Counter - 1 - Question 1

Concept:

For the n-stage ripple counter, the no. of flip-flops used are n.

If Each flip flop is having propagation delay of tp seconds.

Then overall propagation delay of the n-stage ripple counter is 'ntp'

Both of the above diagrams is a 3 stage up counter.

i.e., 3 flip-flops are used.

In order to obtain Q2, the 3 clocks will be used at a different instant or at the instant when each flip flop will get their input.

If each flip flop is having 'tp' as propagation delay, then to get output, the overall propagation Delay will be sum of the propagation Delay of each flip flop.

Explanation:

Given

Ripple counter 4 flip flop 

tp = 20 n second for each flip flop.

T = n tp = total propagation delay

⇒ T = 4 × 20 n sec = 80 n sec

Clock frequency = 

Test: Asynchronous Counter - 1 - Question 2

The number of T flip-flops required to realise a mod-10 asynchronous counter is:

Detailed Solution for Test: Asynchronous Counter - 1 - Question 2

Concept:

For the MOD-N asynchronous counter, the number of T flip-flops is given by:

MOD-N ≼ 2N 

where N = No. of flip-flops

Calculation:

MOD 10 ≼ 2N 

N = 4

Therefore, the number of T flip-flops required to realize a mod-10 asynchronous counter is 4.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: Asynchronous Counter - 1 - Question 3

What is the mod number of asynchronous counter shown (All J = K = 1) below:

Detailed Solution for Test: Asynchronous Counter - 1 - Question 3

Concept:

Counters are characterized by the clock connection & triggering of the clock, as explained below:

Analysis:

  • In the given circuit, each of the JK flip-flops is negative edge triggered & the clock connection is with ‘Q’. So it is an up counter.
  • The output of each flip-flop will be cleared i.e 0 Only when the output from the NAND gate is '0'. So, to get we have to obtain the outputs from flip-flops 2nd,3rd & 4rth as '1' i.e Q4, Q3, Q= 1
  • So when Q4, Q3 & Q2 simultaneously are equal to 1 for the first time, the counter will reset.

So, the sequence of counter states for consecutive clock pulses are as follows:

Here Q4, Q3 & Q2 will be ‘1’ simultaneously for the first time after 28th Clock Pulse is what we observe.

So the given counter is a mode-28 up counter because it can show up in only 28 states.

Test: Asynchronous Counter - 1 - Question 4

Propagation delay of flip flops used for counter design largely affects the speed of operation of

Detailed Solution for Test: Asynchronous Counter - 1 - Question 4

Delay Problem:

  • In asynchronous counters, the output of the previous stage serves as the clock of the next stage.
  • As the number of stages increases the propagation delay of each flip flop stage adds up resulting in the propagation delay to become significant.

The remedy of Propagation delay:

  • To eliminate the propagation delay encountered in different stages, all the flip flops are provided with a common clock (Synchronous Counters).
  • Thus, the output of each stage does not depend on the clock from the previous stage but only on the common clock signal and propagation delay does not add.
Test: Asynchronous Counter - 1 - Question 5

A ripple counter with n flip-flops can function as a

Detailed Solution for Test: Asynchronous Counter - 1 - Question 5

Ripple Counter :

For a ripple counter if the number of flip flops is 'n' then total states are 2n and MOD is 2n 

BCD Counter :

A BCD counter counts 10 states from 0 to 9 

It is MOD 10 counter 

Number of flips required 4 

Ring counter:

A n bit ring counter counts n states and mod is "n"

Johnson Counter:

A n bit Johnson ring counter has 2n states and the mod is 2n

Test: Asynchronous Counter - 1 - Question 6

Which shift register counter required the most decoding circuitry?

Detailed Solution for Test: Asynchronous Counter - 1 - Question 6

Ripple counter: (negative edge)

In a ripple counter using edge triggered JK flip-flops, the pulse input is applied to clock input of one flip-flop. 

A ripple counter requires maximum propagation delay for counting therefore increasing the number of circuits for every count exceeded.

Test: Asynchronous Counter - 1 - Question 7

Maximum count value of a n bit counter is

Detailed Solution for Test: Asynchronous Counter - 1 - Question 7

For a counter with ‘n’ flip flops:

  • The total number of states = 2n (0 to 2n – 1)
  • The largest number that can be stored in the counter = 2n – 1


To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops.

Test: Asynchronous Counter - 1 - Question 8

The number of J-K flip flops in modulo 16 binary up-counter are:

Detailed Solution for Test: Asynchronous Counter - 1 - Question 8

Calculation:

For a Modulo-N counter, which can count to a total of N-states, the number of flip-flops required is:

N ≥ 2n

Govem N = 16

So, 16 =  2n

n = 4

So, the number of J-K flip-flops in Modulo-16 binary up-counter is 4.

Test: Asynchronous Counter - 1 - Question 9

An 8-bit ripple counter and an 8 bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst-case delay in the ripple counter and the synchronous counter be R and S respectively, then 

Detailed Solution for Test: Asynchronous Counter - 1 - Question 9

Concept:

For an n-bit ripple counter, the MSB is generated only when the carry form all the pervious flip-flip are propagated to the MSB flip flop.

So, the maximum time(Worst-Case delay) taken for the output of the Ripple counter to be stable = n × td (where td is the propagation delay of each flip flop) 
        

But in an n-bit synchronous counter, the time taken for the output to be stable is simply the propagation delay of 1 flip-flop i.e. td
        

Calculation:

Given n = 8 bit and td = 10 ns.

For Ripple counter, the worst-case delay = n × tb = 8 × 10 ns = 80 nsec.

For Synchronous-Counter the worst-case delay is td only, which is 10 ns.

Test: Asynchronous Counter - 1 - Question 10

Minimum number of flip flops required for Modulus 15 counter is 

Detailed Solution for Test: Asynchronous Counter - 1 - Question 10

Concept:

For a counter with ‘n’ flip flops:

  • The total number of states = 2n (0 to 2n – 1)
  • The largest number that can be stored in the counter = 2n – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:

Modulus ≤ 2n

Where n is the number of flip-flops.

Calculation:

Number no. of flip – flops are required to construct a mod-15 counter, must satisfy:

2n ≥ 15 i.e.

n = 4

Information about Test: Asynchronous Counter - 1 Page
In this test you can find the Exam questions for Test: Asynchronous Counter - 1 solved & explained in the simplest way possible. Besides giving Questions and answers for Test: Asynchronous Counter - 1, EduRev gives you an ample number of Online tests for practice

Top Courses for Electrical Engineering (EE)

Download as PDF

Top Courses for Electrical Engineering (EE)