Test: Sequential Circuits - 1 - Electrical Engineering (EE) MCQ

Ripple Counter:

For a ripple counter if the number of flip flops is 'n' then total states are 2n and MOD is 2n 

BCD Counter:

A BCD counter counts 10 states from 0 to 9 

It is MOD 10 counter 

Number of flips required 4 

Ring counter:

A n bit ring counter counts n states and mod is "n"

Johnson Counter:

A n bit Johnson ring counter has 2n states and the mod is 2n

Concept:

Lockout free condition: If a counter from an unused state enters one of the used states then the counter is called lock-out free. While taking any unused state as the initial state if the next state comes out to be a used state, the counter is said to be lockout free.

Synchronous counter: A counter in which all the flip-flops are triggered with the same clock pulse. In such counters, if the propagation delay of one flip-flop is tf, then the propagation delay for the whole counter will also be tf

Asynchronous counter: A counter in which all the flip flops are not triggered by the same clock pulse. In such counters, total propagation delay will be equal to the sum of propagation delay for all flip flops.

Calculation:

Given that, propagation delay of each flip-flop = 40 ns

Width of the strobe pulse = 20 ns

Total propagation delay = 40 × 4 + 20 = 180 ns

Maximum clock frequency

Concept:

Overall modulus of a cascaded system is the product of their individual modules.

For example:

A counter of modulus p, modulus q, and modulus r is cascaded, then the modulus of the overall counter is p × q × r

Calculation:

Given, 

The modulus of all three counters is 5

Then the overall modulus = 5 × 5 × 5 = 125

Ring counter:

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

 

A Straight ring counter with ‘n’ flip-flops will have n states.

Johnson counter:

A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.

It is also called a twisted ring counter.

The MOD of the Johnson counter is 2n if n flip-flops are used.

The circuit diagram for a 4-bit Johnson Counter is as shown:

Concept:

The maximum propagation delay (t_pd) for the synchronous counter is given by:

t_pd = t_d

t_d = Propagation delay of 1 Flip flop.

Calculation:

Given is a 4-bit synchronous counter for which the maximum possible time needed for the change of state will be the maximum possible propagation delay:

t_pd = Delay of 1 flip-flop only

t_pd = 15 ns
Important Points

• In synchronous counters, all flip-flops change simultaneously and in asynchronous counters, the propagation delay of the flip-flops add up to produce the overall delay.
• Although synchronous counters usually have more combinational logic, the propagation delay through these gates is small compared to the propagation delay through many stages of flip-flops.
• So the Synchronous counter will provide the least delay compared to Asynchronous counters.

The maximum propagation delay for an n-bit asynchronous counter is given by:

t_pd = n × t_d

Concept:

If we pass the input signal to a single T-flip flop, we will get half of the frequency at the output.


Similarly, when we pass the input signal into an n-bit flip flop counter, the output frequency (f_out) will be:

Application:

Given Input frequency f = 100 Hz

f_out = 12.5 Hz

The Ring shift counter is a recirculating register in which the serial output is connected back to the serial input as shown:

A Straight ring counter with ‘n’ flip-flops will have n states.
Important Points
Johnson Counter:

A Johnson counter is a modified ring counter, where the inverted output from the last flip flop is connected to the input to the first.

The MOD of the Johnson counter is 2n if n flip-flops are used.

The circuit diagram for a 4-bit Johnson Counter is as shown:

Ripple Counter:

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock.

All subsequent flip-flops are clocked by the output of the preceding flip-flop

Parallel Counter:

A parallel counter is a combinational logic circuit that receives a set of binary count signals in parallel and determines the final count after some fixed delay.

Concept:

A n bit counter has 2ⁿ states and can count from 0 to 2n-1

Application:

Given:

n = 6

so it will count from 0 to 2⁶ - 1

= 0 to 63
Important Points

• An n-bit ring counter has n states.
• A Johnson counter has 2n states.
• A ripple counter has 2n states.

Pattern/Sequence detection:

To detect the sequence see only those i/p by which we can move in the forward direction.

 

Overlap/Non-Overlap:

We need to see the last state, after reaching the last state if we use bits of sequence then this will be overlapping, if we directly go to the initial state without using any bit then it will be non-overlapping.

In the question, we can see that at the last we will get sequence 1101101, 

we can use one bit in overlapping, but here we didn't use any bit of the previous detected sequence for detection of the next sequence so it is a non-overlapping type.

From the given circuit diagram,


The output Q_A, Q_B, Q_C is repeating for every 5 clock pulses.

Hence frequency will be divided by 5.