Test: CMOS - 1 - Electrical Engineering (EE) MCQ

TTL stands for Transistor-Transistor Logic and CMOS stands for Complimentary Metal Oxide Semiconductor.

• Complementary Metal-oxide-semiconductor (CMOS) uses complementary & symmetrical pair of P-type & n-type MOSFETS.
• The two important characteristics of CMOS devices are high noise immunity and low power dissipation.
• CMOS devices dissipate less power than NMOS devices because the CMOS dissipates power only when switching (“dynamic power), whereas N channel MOSFET dissipates power whenever the transistor is on because there is a current path from Vdd to Vss.
• In a CMOS, only one MOSFET is switched on at a time. Thus, there is no path from voltage source to ground so that a current can flow. Current flows in a MOSFET only during switching.
• Thus, compared to N-channel MOSFET has the advantage of lower drain current from the power supply, thereby causing less power dissipation.
• The typical quiescent power dissipation of low-power CMOS units is 2 nW

Option(1)- Schottky transistors are  preferred for TTL logic systems. These transistors portray the Schottky effect and thus have higher switching speed in comparison to CMOS logic family.So option 1 is false.

Option(2)- TTL dissipates a lot of power where as CMOS uses almost no power in the static state (that is, when inputs are not changing). So option 2  is false.

Option(3)- TTL  requires more space and isolation in comparison to CMOS logic family. The required silicon area for implementing  CMOS  is very small. So option 3  is true.

Concept
CMOS logic circuit is an extension of a CMOS inverter. It consists of two network transistors, a pull-down network (PDN) constructed of an n-MOS and Pull-up Network (PUN) constructed of P-MOS.

PDN: Since nMOS conducts when the signal gate is high, PDN is activated when the inputs are high.
PUN: It comprises PMOS and conducts when the input signal gate is low.
The PDN and PUN are connected in parallel to form OR logic function and they are connected in series to form AND logic as shown:

General comparison of three commonly available logic families is explained in the following table:

Concept:

• The given circuit contains both NMOS and PMOS. So it is a CMOS implementation.
• For CMOS implementation if NMOS transistors are in series then PMOS transistors corresponding to their NMOS counterparts will be in parallel.
• Similarly, if NMOS transistors are in parallel then PMOS transistors corresponding to their NMOS counterparts will be in series.
• The output will be the negate of the function implemented by the NMOS transistors.

According to De morgan's theorem:

Calculation:

In the given circuit, signals A, B, and C̅  are in series for NMOS implementation. ∴ The output will be:

Concept:
MOS logic circuit consists of two network transistors, a pull-down network (PDN) and a Pull-up Network (PUN) as shown:

The PDN and PUN are connected in parallel to form OR logic function and they are connected in series to form AND logic as shown:

Complementary Metal-oxide-semiconductor (CMOS) uses complementary & symmetrical pair of P-type & N-type MOSFETS.

 

1. The two important characteristics of CMOS devices are high noise immunity and low power dissipation.
2. In CMOS, during static operation at a time, only one MOS is ON i.e. either PMOS or NMOS. So there is no direct path from the power supply to the ground. Hence, Power dissipation in CMOS is low in static operation but it has high power dissipation in dynamic operation.
3. Fanout of CMOS is high. 
4. The gate has an almost ideal voltage-transfer characteristic. The logic swing is equal to the supply voltage and is not a function of the transistor sizes. The noise margins of asymmetrical inverter (where PMOS and NMOS transistors have equal current driving strength) approach VDD/2. The steady-state response is not affected by fanout.

To maximize the switching speed of a logic gate, for example, an inverter, it is best if the rise and fall time of the logic gate’s output signal is the same.

For this to occur, the top side transistors of the logic gate must switch current into the output of the logic gate at the same magnitude as the low side transistors.

Since PMOS transistors (high side) have approximately half the mobility of NMOS transistors (low side), it is necessary to add two parallel PMOS devices to the high side to achieve the equivalent magnitude currents.

In saturation
NMOS:

C_ox and voltage are the same for both side, when 


Considering the same length as it is a fixed constraint for the circuit.

that’s why we take PMOS size greater than N-MOS

Concept:

Calculation:

“We can get the answer either by using NMOS configuration OR by PMOS configuration”
Hence, we taking NMOS configuration:
∵ A and B is in parallel ⇒ A + B
A and B combinedly is in series with “C” ⇒ (A + B) C
A, B, C combinedly in parallel with “D” ⇒ (A + B) ⋅ C + D