Test: Flip-Flops - Computer Science Engineering (CSE) MCQ

Concept:
For a counter with ‘n’ flip flops:

• The total number of states = 2ⁿ (0 to 2ⁿ – 1)
• The largest number that can be stored in the counter = 2ⁿ – 1

To construct a counter with any MOD number, the minimum number flip flops required must satisfy:
Modulus ≤ 2n
Where n is the number of flip-flops and is the minimum value satisfying the above condition.
Note: A MOD-N counter is also called a divide by N counter as the input frequency is divided by the number of states of the counter.

Calculation:
Number no. of flip – flops are required to construct mod-16 counter, must satisfy:
2n ≥  16
The minimum value of n satisfying the above is:
n = 4 bits

Race around condition:
For JK flip-flop if J, K, and Clock are equal to 1 the state of flip-flop keeps on toggling which leads to uncertainty in determining the output of the flip-flop. This problem is called Race around the condition.

This can be eliminated by using the following methods.

• Increasing the delay of flip-flop
• Use of edge-triggered flip-flop
• Use of master-slave JK flip flop

The Master-slave configuration is used in a flipflop to eliminate the race around condition but not to store two bits of information.

RS-232 only allows for one master and one slave and is limited to distances of up to 15 meters.

Key Points
RS-232, RS-422, and RS-485 are standards for serial communications that define the pinouts, cabling, signal levels, transmission baud rates, and parity checking.

• RS-232 only allows for one master and one slave and is limited to distances of up to 15 meters.
• RS-422 can address up to 10 slaves using four wires (full duplex) and has a distance capacity of 4000 feet.
• RS-485 can address up to 32 slaves using either a two-wire (half duplex) or a four-wire system (full duplex) and has a distance capacity of 4000 meter.

The cross-coupled connections from the output of one gate to the input of the other gate constitute a feedback path. For this reason, the circuits of NOR based S-R latch classified as asynchronous sequential circuits. Moreover, they are referred to as asynchronous because they function in the absence of a clock pulse.

The output of latches will remain in set/reset untill the trigger pulse is given to change the state.

The basic latch consists of two inverters. It is in the sense that if the output Q = 0 then the second output Q’ = 1 and vice versa.

There are two type of sequential circuits viz., (i) synchronous or clocked and (ii) asynchronous or unclocked. Synchronous Sequential Circuits are triggered in the presence of a clock signal, whereas, Asynchronous Sequential Circuits function in the absence of a clock signal.

In sequential circuits, the output signals are fed back to the input side. So, The circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called sequential circuits. Unlike sequential circuits, if output depends only on the present state, then it’s known as combinational circuits.

In D flip flop, when the clock is high then the output depends on the input otherwise reminds previous output. In a state of clock high, when D is high the output Q also high, if D is ‘0’ then output is also zero. Like SR flip-flop, the D-flip-flop also have an invalid state at both inputs being 1.

The SR flip-flop actually has three inputs, Set, Reset and its current state. The Invalid or Undefined State occurs at both S and R being at 1.