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GATE Mock Test Electronics Engineering (ECE)- 3 - Electronics and Communication Engineering (ECE) MCQ


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30 Questions MCQ Test - GATE Mock Test Electronics Engineering (ECE)- 3

GATE Mock Test Electronics Engineering (ECE)- 3 for Electronics and Communication Engineering (ECE) 2024 is part of Electronics and Communication Engineering (ECE) preparation. The GATE Mock Test Electronics Engineering (ECE)- 3 questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The GATE Mock Test Electronics Engineering (ECE)- 3 MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for GATE Mock Test Electronics Engineering (ECE)- 3 below.
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GATE Mock Test Electronics Engineering (ECE)- 3 - Question 1

A vendor sells his articles at a certain profit percentage. If he sells his articles at 1/4th of his actual selling price then he incurs a loss of 60%. What is his actual profit percentage?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 1
Let the cost price = 100 Rs.

From the options:

If profit % = 60%

Then SP = 160 Rs.

New SP = 160/4 = 40 Rs.

Then,

Percentage loss= (100-40)/100 = 60%

Hence Verified

ALTERNATE:-

Let the selling price is 100

New selling price 100/4 = 25

He suffers a loss of 60%.

CP × 0.4 = 25

CP = 25/0.4 = 62.5

Actual Profit = 100 - 62.5 = 37.5

profit% = 37.5/62.5 × 100 = 60%

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 2

Directions: In the following question, a set of three figures X, Y and Z shows a sequence in which a piece of paper is folded and finally cut from one or more sections. Below these figures, a set of answer figures marked (a), (b), (c) and (d) shows the design which the paper actually acquires when it is unfolded. You have to select the answer figure which most closely resembles the unfolded piece of paper.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 2
After the paper is unfolded, the following pattern will be observed

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GATE Mock Test Electronics Engineering (ECE)- 3 - Question 3

Criteria for selecting candidate for internship programme

The candidate:

  1. can preferably start the internship between 18th Oct'17 and 17th Nov'17

  2. are preferably available for duration of 6 months

  3. have computer skills and interest in designing

  4. have already graduated or are currently in any year of study

  5. knows how to deal with customers Nick is a high school student and wants to do an internship as his summer project. He is a very vibrant boy and goes well with people.

Is he the right candidate for the internship?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 3
He is looking for summer internships and November is not summer time.
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 4

In a certain code, BRAIN is written as * % ÷ # x and TIER is written as $#+%. How is RENT written in that code?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 4

The code for RENT is %+×$.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 5

Which of the following is MOST OPPOSITE in meaning to Locus?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 5
Locus (noun) -a particular position or place where something occurs or is situated
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 6

Directions: The table lists the size of building lots in the Orange Grove subdivision and the people who are planning to build on those lots. For each lot, installation of utilities costs $12,516. The city charges impact fees of $3,879 per lot. There are also development fees of 16.15 cents per square foot of land.

How much land does Mr. Taylor own in the Orange Grove subdivision?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 6
Look at the chart to see all of the land he owns

The total amount of land he owns is, 8023 + 9004 + 8269 + 6774 = 32070 square feet.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 7

The Union Sports Ministry has approved five lakh rupees from the National Welfare Fund for Sportspersons for Kaur Singh who is suffering from heart disease. Kaur Singh is associated with which of the following sports?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 7
Kaur Singh, former heavyweight Boxer is struggling with the treatment for heart disease and admitted at private hospital in Mohali. Under such circumstances, the Union Sports Ministry has approved five lakh rupees from the National Welfare Fund for Sportspersons for Kaur Singh.
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 8

Two positions of a dice are given. Which of the following numbers would be at the top when 2 is at the bottom?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 8
Number 3 appears in the same position both times.

The pattern of numbers is as given below.

From first orientation, write the numbers in clockwise direction.

3 - 5 - 2

From second orientation, write the numbers in clockwise direction.

3 - 1 - 6

Hence, 2 is opposite to number 6 and 5 is opposite to number 1.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 9

Direction: In given question below there are three statements followed by two conclusions numbered I and II. You have to take the given statements to be true even if they seem to be at variance with commonly known facts. Read all the conclusions and then decide which of the given conclusion logically follows from the given statements disregarding commonly known facts.

Statements:

All oils are sands

Some clays are oils

All clays are rocks

Conclusions:

  1. Atleast some clays are sands
  2. Some oil is not rock
Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 9

Statements

All oils are sands

Some clays are oils

All clays are rocks

Combining all three statements, we get

Conclusions

  1. At least some clays are sandsü
  2. Some oil is not rockû

 

Conclusion 1

Some clays are oils + All oils are sands = Some clays are sands

Hence, Thus, conclusion I follows.

Conclusion 2

Some clays are oils→ conversion → some oils are clays + All clays are rocks = Some oils are rock. Hence, conclusion 2 does not follows.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 10

Walking at th of his usual speed, a man reaches his destination two minutes early. What is the time taken by him to cover the same distance at his usual speed?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 10
The ratio of speeds before and after is 10 : 11. The ratio of time will be 11 : 10.

or,

He takes 1 unit less time now which is given as 2 minutes. The time taken will be 22 minutes at his usual speed.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 11

Given a network with values of components depicted in the figure.

Find the sum of current through 5Ω and 4Ω resistor.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 11
Assume the current in the first loop be I1 and in the second loop be I2.

Then, we can apply mesh analysis to solve it.

Mesh 1: 15I1-10I2 = 5

Mesh 2: -10I1+ 20I2 =10

On solving them, we have

I1 = 1A

I2 = 1A

Thus, sum = 2A

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 12

Which of the following is correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 12

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 13

Given the following system

T{X[n]} = X[n] + 3u[n+1]

Where u[x] represents unit step functions-

Which of the following is a correct representation of the system?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 13
We have,

T{X2[n] + X1[n]} = X1[n] + X2[n] +3u[n+1]

And

T{X1[n]} = X1[n] + 3u[n+1]

T{X2[n]} = X2[n] + 3u[n+1]

Since,

T{X2[n] + X1[n]} ≠ T{X1[n]} + T{X2[n]}

Thus, system is non linear.

T{X[n-no]} = X[n-no] + u[n+1]

≠ y[n-no]

Thus, system is Time Variant.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 14

The width of the depletion layer is proportional to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 14
A depletion region consists of immobile charge carriers such as positive ions and negative ions. The mobile charge carriers such as free electrons are absent in depletion region. The p-side of the depletion region has negative ions and n-side of the depletion region has positive ions.

When doping is kept high in P-N junction, then there will be less space for electrons to travel.

Depletion width is non linearly and inversely proportional to the doping;

W ∝ 1/(√doping)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 15

List-1 (pole location) with list-2(shown constant amplitude with impulse response).

Select the correct answer using the codes given below.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 15
For A

If we plot A then it is similar to the 4 which is followed by equation K1+K2e-at+K3eat

For B

If we plot B then it is similar to the 1 which is followed by equation (sinat +sinbt) u(t)

For C

If we plot c then it is similar to the 3 which is followed by equation eatsinbt u(t)

For D

If we plot D then it is similar to the 2 which is followed by equation sinat u(t)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 16

For the latch circuit shown below, which of the following options is correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 16

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 17

In a PCM system, if the code word length is increased from 6 to 8 bits, the signal to quantization noise ratio improves by the factor

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 17
When word length is 6

(S/N)N=6 = 22×6 = 212

When word length is 8

(S/N)N=8 = 22×8 =216

now (S/N)N=8/(S/N)N=6 = 216/212 = 24 =16

Thus it improves by a factor of 16.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 18

The far field of an antenna varies with distance r as

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 18
The far field is the region far from the antenna, as you might suspect. In this region, the radiation pattern does not change shape with distance.

Far field is inversely proportional to distance r.

Far field ∝ 1/r

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 19

A semiconductor sample at room temperature has an intrinsic concentration of 2.5 X 1017 /m3. After doping what will be the minority carrier concentration if the majority carrier concentration is given as 5.5 X 1021 /m3.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 19
In a pure Semiconductor (Intrinsic Semiconductor), the electron and hole concentrations are n1p1 respectively. By doping impurity atoms the SC becomes extrinsic then the electrons and hole concentrations n2p2 respectively, then the following equations are acceptable

n1p1 = n2p2 = ni2

For Intrinsic Semiconductor, n=p=ni2 and as per questions before doping n1p1=ni2

Therefore,

p2=ni2n2

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 20

If the block diagram shown in figure 'A' and figure 'B' are equivalent, then x in figure 'B' will be equal to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 20

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 21

For an ideal p-channel MOSFET, μp= 300cm2/v-s, W = 15μm, L = 1.5μm, tox = 300A, Vt = -0.7V. If the transistor is non-saturation region at VSD=0.5V, then what is the Transconductance gm?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 21
ID = (μpCox/2)(W/L)(2(VSG+VT)VSD-VSD2)2 ,

where

Cox = (3.9x85x1014)/(300x1010).

Cox = 1.15x10-7 F/m2. Also, gm =∂(ID)/∂(VSG).

On substituting and solving, gm = 0.172mS.

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 22

Which of the following is/are s-domain equivalent of the circuit shown below?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 22
For an inductor, time-domain to s -domain transformation is shown as,

or

For t < 0="" />

i(0) = 10 mA

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 23

From the circuit given below, find out the operating region of the transistors T1 and T2

(VTH = -0.4)

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 23
For T1

VSD = VS – VD = 1.5 – 0 = 1.5 V

VSD(sat)=VSG+VTH=(1.5−0.5)−0.4

= 1 – 0.4 = 0.6V

Here, VSG > (VTH) & VSD > VSD(sat)

So, T1 is in Saturation region

Similarly for T2,

VSD = VS−V0= 0.9−0.9 = 0

VSD(sat)=VSG+VTH= (0.9 − 0) − 0.4 = 0.5V

Here VSDSD(sat) & VSG>(VTH)

∴ T2 in linear region

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 24

Consider the following CT systems with an input x(t) and output y(t).

System P : y(t) = dx(t)/dt

System Q : y(t) = ex(t)

System R : y(t) = 3x(t)

System S : y(t) = 3x(t) + 5

Which of the above system is/are linear?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 24
System P

(System P is linear)

System Q:

(System Q is not linear)

System R:

= ay1(t) + by2(t) (System R is linear)

System S:

(System S is not linear)

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 25

A communication channel having AWGN characteristics is operating in such a way that SNR >> 1. The bandwidth of signal being transmitted is B and capacity C1. Determine the capacity of channel if a signal with half the bandwidth is transmitted through the same channel with same quality.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 25
Here same quality implies that SNR for transmitted signals is kept equal. We have a formula for channel capacity as

C1=B1log2⁡(1+S/N)

Now, B2 = 0.5 × B1. SNR is same, thus C2 would be,

C2 = 0.5 * B1log2(1 + S/N) = 0.5 * C1

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 26

In the following scheme, if the spectrum M(f) of m(t) is as shown, then the spectrum Y(f) of y(t) will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 26
The block diagram is as shown below

All waveform is shown below

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 27

An amplifier operating over the frequency range of 18 to 20 MHz has a 10kΩ input resistance.The RMS noise voltage at the input to the amplifier at ambient temperature is (assume Boltzman’s constant = 1.38 × 1023J/K)

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 27

GATE Mock Test Electronics Engineering (ECE)- 3 - Question 28

Consider two functions x = ψ ln Φ and y =Φ In ψ . Which of the following is the correct expression for ∂ψ/∂x ?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 28
x = ψ ln Φ ⇒ ψ = x/ln Φ….(i)

y =Φ In ψ ⇒ Φ = y/In ψ

Putting value of Φ in (i), we get

Assuming y constant and differentiating ψ with respect to x.

Putting value of ( In y - In(In ψ)) = x/ψ from equation (ii) in equation (iii), we get

(Replacing x by Φ in ψ)

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 29

What is the maximum torque (in Nm) on a square loop of 200 turns in a field of uniform flux density of 1 Wb/m2. The loop has 15cm side and carries a current of 5A.


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 29
Max torque, Tmax = NBIS

N-no of turns = 200

B = 1 Wb/m2

I = 5A

S-area of loop = (15x10-2)2 = 0.0225

Tmax = 200×1×5×0.0225 = 22.5Nm

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 3 - Question 30

The sampling rate for Compact Discs (CDs) is 44,000 samples/s. If the samples are quantized to 256 levels and binary coded, the corresponding bit rate (in bits per second) is ______.(Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 3 - Question 30
Given,

Sampling Rate = 44,000 Samples / sec

Number of Quantization levels = 256.

No. of Bits required for each sample = log2256 = 8 bits/sample.

This we got under the assumption that all levels are equiprobable.

Thus bit rate = 8 bits/sample X 44,000 Samples/sec = 3,52,000 bits/sec

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