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GATE Mock Test Electronics Engineering (ECE)- 5 - Electronics and Communication Engineering (ECE) MCQ


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30 Questions MCQ Test - GATE Mock Test Electronics Engineering (ECE)- 5

GATE Mock Test Electronics Engineering (ECE)- 5 for Electronics and Communication Engineering (ECE) 2024 is part of Electronics and Communication Engineering (ECE) preparation. The GATE Mock Test Electronics Engineering (ECE)- 5 questions and answers have been prepared according to the Electronics and Communication Engineering (ECE) exam syllabus.The GATE Mock Test Electronics Engineering (ECE)- 5 MCQs are made for Electronics and Communication Engineering (ECE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for GATE Mock Test Electronics Engineering (ECE)- 5 below.
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GATE Mock Test Electronics Engineering (ECE)- 5 - Question 1

The given question is followed by two statements: select the most appropriate option that solves the question

Capacity of a solution tank A is 70% of the capacity of tank B. How many gallons of solution are in tank A and tank B?

Statements:

  1. Tank A is 80% full and tank B is 40% full

  2. Tank A if full contains 14,000 gallons of solution

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 1
Statement 1 can be used to solve the question if capacity of both tanks is already known

Statement-2 can be used if it is known what quantity of each tank is full/empty.

Therefore, by using both statements

Let capacity of tank B is x

70/100x = 14000

= x = 20000 gallons

Solution in tank A = 80/100 × 14000

= 11200 gallons

Solution in tank A = 40/100 × 20000

= 8000 gallons

∴ Total solution = 11200 + 8000

= 19200 gallons

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 2

Which of the following is the antonym of the word SILENCE?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 2
Silence refers to 'no speech'. Babble means continuous, and sometimes incoherent speech.
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GATE Mock Test Electronics Engineering (ECE)- 5 - Question 3

What is the value of the following expression?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 3
The given expression is

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 4

Which of the following is the synonym of the word ADMONISH?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 4
Admonish means taking someone to task for wrong doing. This is similar to warning or cautioning someone for some wrong doing.
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 5

From a group of 61 students, each student appears for at least one of the 3 papers i.e.

GATE, ESE or SSC. Out of the students appearing for SSC, the number of students appearing for ONLY SSC is equal to the number of students who also appear for GATE.

The number of students who appear for only GATE is 3 more than the number of students who appear for all 3; number of students appear for ESE alone is higher than the previous number by 5.

If 32 students appear for ESE and 36 students appear for exactly ONE exam, then the number of students appearing for all 3 exams are _____.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 5

Base on the diagram and information available,

c = f + g …(i)

a + b +c = 36

⇒ d + e + f + g = 61-36 = 25 …(ii)

a + b + c = 36

⇒ g + 3 + g + 8 + c = 36

⇒ 2g + c = 25 = 3g + f …(iii)

∵ b + d + e + g = 32

⇒ g + 8 + d + e + g = 32

⇒ d + e + g + g = 24

⇒ d + e + f + g + g = 24 + f = 25+g

⇒ f = g +1

∵ 3g + f = 25

⇒ 4g = 24

∴ g = 6

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 6

Which of the following statements cannot be inferred from the passage?

Not stagnating moment to moment is called achievement. Inward humility is achievement, outward courtesy is virtue. Establishing myriad truth in your nature is achievement; the mind being essentially detached from thoughts is virtue. Not departing from one's essential nature is achievement; acting adaptively without being affected is virtue. Continuity moment to moment is achievement; balance and directness of mental activity are virtue. Refining your own nature is achievement. Refining your own person is virtue.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 6
Going through the passage,

(1) is eliminated as it is true as per line,' Inward humility is achievement, outward courtesy is virtue' of the passage.

(2) is true as per the line ,'Refining your own nature is achievement. Refining your own person is virtue'. Hence, eliminated.

(3) can also be inferred in the last lines.

(4) is the only statement that can not be inferred,

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 7

A water tank of capacity 6000 litres is connected to 2 taps ’A’ and 'B'. Water flows from these 2 taps at 90 litres per minute and 60 litres per minute respectively.

To fill this empty tank, first tap ‘A’ is opened for sometime and once it is closed, tap ‘B’ is opened till the tank is full taking a total of 90 minutes.

What is the difference in the time (in minute) for which the taps are opened to fill the tank.

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 7
Let the tap B is open for time = t1 minute.

duration of tab A is opened for '90-t1' minute.

Since the rate of inflow of water of tab A is 90 liter/minute, while the rate of inflow of water of tab B is 60 liter/minute.

So as per the given data they both fill the tank as follow

90×(90-t1) + 60 x(t1) =6000

8100-6000 = 30 t1

t1 = 2100/30 = 70 Minute

Hence Tab B is opened for 70 Minute.

It is already given that the total time of open for both tab is 90 Minute hence the duration for which Tab A is open = 90-70 = 20 Minute

Difference in time = 70-20 = 50 Minute.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 8

1/38 + 1/39 + 1/39 + 1/39 is equal to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 8
Remember that you can only add fractions with the same denominator.

Rearrange 1/38 so that it can be added to 1/39 . That is, try and turn 1/38 into a fraction with 39 in the denominator.

Multiply 1/38 by 3/3 to get

Solving,

Canceling out a factor of 3 gives,

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 9

Which one of the following describes the relationship among the three vectors,

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 9
From the question we get

Solving this we get to know,

Vectors are linearly independent.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 10

What will be the sum of the factors of 3129?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 10
N is a number such that N = ap x bq x cr ... where a, b, c are prime number and p, q, r are positive integers.

So, sum = ;

Here a = 3, p = 129,

So required sum =.(3130 - 1)/2

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 11

The circuit below is at steady state

The sum of currents i1 and i2 (in A) is_____


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 11
Drawing equivalent circuit at steady state

Since now 25Ω and 10Ω are in parallel with 50V.

i1 = 50/10 = 5A

i2 = 50/25 = 2A

i1 + i2 = 7A

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 12

The transition capacitance of a diode is proportional to

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 12
If reverse bias voltage increases, width of the depletion layer increases and hence capacitance decreases. For a step graded junction, the width of the depletion region, W is inversely proportional to the square root of the reverse bias voltage.
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 13

The Fourier transform of the signal shown in the following figure is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 13
The given signal is x(t) = u(t+1) – u(t-4)

Differentiating both sides

d/dtx(t) = δ(t + 1) - δ(t - 4)

Taking Fourier transform on both sides

jω × (jω) = e − e−jω

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 14

In the J-K flip-flop, we have J = Q̅ and K = 1 as shown in the figure:

Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 14
For the circuit given,

Counting from MSB to LSB, the output will be 010101.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 15

A system is described by dy(t)/dt + 3y(t) = x(t) where x(t) is input and y(t) is output. Then the unit step response of the system is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 15
dy(t)/dt + 3y(t) = x(t)

Taking laplace transfarm

sY(s) + 3Y(s) = X(s)

Y(s) = X(s)/(s+3)

Given x(t) = u(t) ⇒ X(s) = 1/s

Y(s) = 1/s(s+3) = 1/3(1/s − 1/s+3)

Y(t) = 1 - e-3t/3

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 16

The state space equation of a system is described by

x = Ax + Bu

y = Cx

Where x is state vector, u is input, y is output and A =

A unity feedback is provided to the above system G(s) to make it a closed loop sytem as shown in figure.

For a unit step input r(t), the steady state error in the output will be

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 16
Steady state error is given by,

Here R(s) = (unit step input)

G(s) = 1/s(s + 2)

H(s) = 1 (Unity feed back)

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 17

The Transfer function in relation to Bode Plot given below is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 17
Sol. Starting slope of Bode Plot is –40 db/d

∴ It has term K/S2

As the initial slope intersect at w = 5

K = w2

K = 25

New for corner frequency wcf1 = 2 slope changes to –20 db/d

∴ It has zero in the transfer function having time constant

T1 = 1/ωcf1 = 1/2 = 0.5

For corner frequency cos⁡f2 = 10,slope changes from –20 db/d to – 40 db/d

∴ It contain in the transfer function having time constant

T2 = 1/ωcf2 = 0.1

∴ Transfer function = 25(1 + 0.5S)/S2(1 + 0.1S)

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 18

The Fourier series expansion of a real periodic signal with fundamental frequency f0 is given by gp(t) = . It is given that C3 = 3 + j5. Then, C-3 is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 18
Here, C3 = 3 + j5

For real periodic signal,

C-k = Ck*

Thus, C-3 = 3 - j5

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 19

Consider a spring-mass system given as where m stands for mass, c for the damper, and spring labelled as k

In the figure shown above, consider the m= 1 units, k= 6 units, c= 8 units.

Sum of all the poles and zeroes of the transfer function is:

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 19
F is the sum of the forces, and here the spring and the damper are acting in opposite directions so. Force of Spring - Force of Damper = F

fu is substituted for x and therefore duedx Separation of variables gives the next equation m(d2y/dt2) + c(dy/dt) + k(y) = c(du/dt) + k(u)

Now the function is ready to be transformed from the time domain into the frequency domain. The Laplace of d2y/dt2 and dy/dt are as follows:

L(f′′) = s2L{f) − sf(0) − f′(0)

L(f′) = s.L(f) − f(0)

Assuming zero initial conditions the equations are (m(s2) + c(s) + k)⋅Y(s) = {c(s) + k)∪(s)

Let the transfer function G(s) is defined by \Upsilon(s) / U(s\) G(s) = {c(s) + k)/(m(s2) +c(s) + k)

Substituting the values in the G(s) G(s) = (8s + 6)/(s2 + 8s + 6)

⇒ (8s + 6)/(s + 4)(s + 2)

From the numerator we have would give you a zero at s= - 3/4 and solving for s in the denominator gives poles at s = -4, -2

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 20

Consider the following circuits:

  1. Full adder

  2. Half adder

  3. JK flip-flop

  4. Counter

Which of the above circuits are classified as sequential logic circuits?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 20
Full adder and Half adder circuits are combinational circuits. JK flip-flop and counter are sequential circuits.
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 21

The CMOS circuit shown below implements the logic function

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 21
Operation of circuit is given below

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 22

Path of a charged particle A that enters in a uniform magnetic field B (pointing into the page) is shown in the figure.

The deflection in the path of the particle shows that the particle is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 22
Force applied by a magnetic field B on a moving charge with velocity v is defined as,

F = v x B

Since the direction of velocity v and B are perpendicular to each other as obtained from the figure shown, the resultant force will be perpendicular to both of them, i.e. the force on the moving charged particle will be in an upward direction. And as the particle is also deflected in an upward direction with the applied force, so it gives the conclusion that the particle will be positively charged.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 23

The circuit shown in figure is best described as a

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 23
This circuit having two diode and capacitor pair in parallel, works as voltage doubler.
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 24

A J-K flip-flop can be made from an S-R flip-flop by using two additional

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 24
In FF conversion, both S and R will be functions of actual external inputs (J and K) and previous O/P.

S = f1(J, K, Qn) and R = f2(J, K, Qn)

Steps:

1. List all possible combinations of J, K and Qn (000 to 111, first three columns).

2. Fill the values of Qn+1 using JK FF truth table (4th column).

3. Now, we have Qn and Qn+1 ready, so fill the values of S and R using SR excitation table.

Using K map to simplify S and R:

S = JQn and R = KQn

So, two additional AND gates required.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 25

A Mealy system produces a 1 output if the input has been 0 for at least two consecutive clocks followed immediately by two or more consecutive 1’s. The minimum state for this system is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 25
The state diagram is as shown below

There are 4 minimum state.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 26

Let P and Q be square matrices such that PQ = I, then zero is an eigen value of

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 26
We have PQ = I

Or Q = P-1 = or P = Q-1

If zero is an eigen value of any of the matrix, then other matrix will have infinity as an eigen value.

Thus, zero is not an eigen value of either P or Q.

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 27

The value of ∫c|z|dz, there 'C' is the left half of the unit circle, is

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 27
Given C: |Z| = 1

⇒ z = e

⇒ dz = e

and θ : π/2 to 3π/2

⇒ I = ieiθ(3π/2) - e(π/2)

∴ I = -2i

GATE Mock Test Electronics Engineering (ECE)- 5 - Question 28

In a discrete-time complex, exponential sequence of frequency ω0 = 1, the sequence is:

  1. Periodic with period 2π/ω0

  2. Non periodic

  3. Periodic for some value of period N

Which of the above statements is/are correct?

Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 28
ω0 = 1

A discrete time complex exponential is periodic if ω0/2π is a rational number. But given ω0 = 1

ω0/2π = 1/2π = is a irrational number, so it is non periodic.

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 29

Given L−1[4/s2+2s] find


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 29

Applying L Hospital rule because its 0/0 form

*Answer can only contain numeric values
GATE Mock Test Electronics Engineering (ECE)- 5 - Question 30

A germanium sample at T = 300 K is doped with donor atoms with concentration Nd = 6 x 1018/cm3. At thermal equilibrium, if the intrinsic concentration of the sample is ni = 2.4 x 1013/cm3, then the hole concentration/cm3 is ___ × 106 (Answer up to the nearest integer)


Detailed Solution for GATE Mock Test Electronics Engineering (ECE)- 5 - Question 30
n0p0 = n2i

n0 ≈ ND

p0 = (2.42 x 1026)/(6 x 1018) = 0.96 × 108/cm3 = 96 × 106/cm3

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