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Test: Digital Electronics- 2 - Electrical Engineering (EE) MCQ


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20 Questions MCQ Test - Test: Digital Electronics- 2

Test: Digital Electronics- 2 for Electrical Engineering (EE) 2024 is part of Electrical Engineering (EE) preparation. The Test: Digital Electronics- 2 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Digital Electronics- 2 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Digital Electronics- 2 below.
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*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 1

In the circuit sho

Qo = Q1 = 0 Then the values of QO and QI after 335th clock pulse are _____________


Detailed Solution for Test: Digital Electronics- 2 - Question 1

It is a MOD - 4 counter, because Johnson counter =

Test: Digital Electronics- 2 - Question 2

An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.

What is value of output voltage V0 for switch status so = 0, s1= 1, s2 = 1.

 

Detailed Solution for Test: Digital Electronics- 2 - Question 2

Test: Digital Electronics- 2 - Question 3

An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.

Q. What is the step size of DAC.

Detailed Solution for Test: Digital Electronics- 2 - Question 3

Step size

Test: Digital Electronics- 2 - Question 4

For the given circuit shown in figure signal generated at the output of AND gat is Y. there clock has signal frequency of 4 kHz, with duty cycle 50%

Q. What is the value of frequency of output Y

Detailed Solution for Test: Digital Electronics- 2 - Question 4

A FF is simply MOD-2 counter.

Test: Digital Electronics- 2 - Question 5

The following waveform pattern is for a(n) ________.

Test: Digital Electronics- 2 - Question 6

The input X for count sequence 0, 2, 3, 1, 0, 2 ....

Detailed Solution for Test: Digital Electronics- 2 - Question 6

Just Solve by K-Map.

Test: Digital Electronics- 2 - Question 7

 For a Flip-flop formed from 2 NAND gates as shown in figure, the unusable state corresponds to

Detailed Solution for Test: Digital Electronics- 2 - Question 7

when both X = Y = 0 then value of Q & will remain same so unstable.

Test: Digital Electronics- 2 - Question 8

In the figure as long as XI = 1 and X2 = 1 the output Q remains at

Detailed Solution for Test: Digital Electronics- 2 - Question 8

As long as X1 = 1 and X2 = 1
Since the output is feedback to input NAND gate. It means output is toggle between 0 → 1 → 0 → 1…… makes the output Q unstable.

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 9

The Minimum no. of 2 inputs NAND gate required to implement Boolean function f(A, B, C, D) =

ABCD are_______


Detailed Solution for Test: Digital Electronics- 2 - Question 9

Correct Answer :- 3

Explanation :  

Test: Digital Electronics- 2 - Question 10

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. If by use of K-Map function is minimized in sum of product forms then SOP is

Detailed Solution for Test: Digital Electronics- 2 - Question 10

Test: Digital Electronics- 2 - Question 11

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. Above Minimised SOP, can be implemented by how many minm no. of 2 input NAND gate.

Detailed Solution for Test: Digital Electronics- 2 - Question 11

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 12

Consider the following data in respect of a certain digital gate

loH = 0.2 mA I1H= 40μ.A, 10L = 16 mA, liL = 1.6 mA symbols have their meaning. Fan out will be    


Detailed Solution for Test: Digital Electronics- 2 - Question 12

F.0 = = 5

Smalls of both will be Fan out

F.I = =10

Test: Digital Electronics- 2 - Question 13

If x, y and z are three Boolean variables, then F(x,y,z) = x + xy + y + yz + z + xz is equivalent to

Test: Digital Electronics- 2 - Question 14

How many AND gates are required for a 1-to-8 multiplexer?

Detailed Solution for Test: Digital Electronics- 2 - Question 14

The number of AND gates required will be equal to the number of outputs in a demultiplexer.

Test: Digital Electronics- 2 - Question 15

The logic circuit shown in figure is :

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 16

In a dual slope ADC if reference voltage is 100 mV and the first integration period is set as 50 msec.

For an input voltage of 120 mV, the second integration (de-integration) period is___ ms


Detailed Solution for Test: Digital Electronics- 2 - Question 16

t = 60 m sec

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 17

In a dual slope type digital voltmeter, an unknown signal voltage is integrated our 100 cycles of clock. If the signal has a 50 Hz pick up the maximum clock frequency can be__ kHz


Detailed Solution for Test: Digital Electronics- 2 - Question 17

50 x 100

Test: Digital Electronics- 2 - Question 18

In circuit given if both Transistors have same VT what is the approximate value of highest possible output voltage vout if vh, can range from 0 to VDD, it is assumed that 0 < vT < VDD

Test: Digital Electronics- 2 - Question 19

In the I.C. logic gate shown in figure.

If threshold voltage VBE is o.75 volt and VCE (sat) = 0.2 V, calculate. Value of output voltage

Q. If VA = VB = 4.5 volt

Detailed Solution for Test: Digital Electronics- 2 - Question 19

It is A NAND gate and if VA= VB = 4.5
Then o/p will be logic zero, as both are logic high

SO V0 = VCE, sat = 0•2v

Test: Digital Electronics- 2 - Question 20

If VA = 4.5 volt, VB = 0.2 volt

Detailed Solution for Test: Digital Electronics- 2 - Question 20

if VA = 4.5v & VB = 0.2 v
so o/p will be 1, ie. Vo = 5 volt

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