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Test: Digital Electronics- 2 - Electrical Engineering (EE) MCQ


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20 Questions MCQ Test - Test: Digital Electronics- 2

Test: Digital Electronics- 2 for Electrical Engineering (EE) 2025 is part of Electrical Engineering (EE) preparation. The Test: Digital Electronics- 2 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Digital Electronics- 2 MCQs are made for Electrical Engineering (EE) 2025 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Digital Electronics- 2 below.
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Test: Digital Electronics- 2 - Question 1

An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.

What is value of output voltage V0 for switch status so = 0, s1= 1, s2 = 1.

 

Detailed Solution for Test: Digital Electronics- 2 - Question 1

Test: Digital Electronics- 2 - Question 2

An R — 2R ladder type DAC is shown in Figure if a switch status is '0', then 0 volt is applied and If a switch status is '1' then 5 volt is applied to the corresponding terminal of DAC.

Q. What is the step size of DAC.

Detailed Solution for Test: Digital Electronics- 2 - Question 2

Step size

Test: Digital Electronics- 2 - Question 3

For the given circuit shown in figure signal generated at the output of AND gat is Y. there clock has signal frequency of 4 kHz, with duty cycle 50%

Q. What is the value of frequency of output Y

Detailed Solution for Test: Digital Electronics- 2 - Question 3

A FF is simply MOD-2 counter.

Test: Digital Electronics- 2 - Question 4

The following waveform pattern is for a(n) ________.

Test: Digital Electronics- 2 - Question 5

Consider the partial implementation of a 2 — bit counter using T flip-flops following the sequence 0 — 2 — 3 — 1 — 0, as shown below.


To complete the circuit, the input X should be 

Detailed Solution for Test: Digital Electronics- 2 - Question 5

Sequence is  0 — 2 — 3 — 1 — 0 
From the given sequence, we have state table as

Now we have present state and next state, use excitation table of T flip-flop


Correct option: a) Q Q2

Test: Digital Electronics- 2 - Question 6

 For a Flip-flop formed from 2 NAND gates as shown in figure, the unusable state corresponds to

Detailed Solution for Test: Digital Electronics- 2 - Question 6


Test: Digital Electronics- 2 - Question 7

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. If by use of K-Map function is minimized in sum of product forms then SOP is

Detailed Solution for Test: Digital Electronics- 2 - Question 7

Test: Digital Electronics- 2 - Question 8

The 4 variable function f is given in terms of min term as f(A, B, C, D) = E(2,3,8,10,11,12,14,15)

Q. Above Minimised SOP, can be implemented by how many minm no. of 2 input NAND gate.

Detailed Solution for Test: Digital Electronics- 2 - Question 8

Test: Digital Electronics- 2 - Question 9

If x, y and z are three Boolean variables, then F(x,y,z) = x + xy + y + yz + z + xz is equivalent to

Test: Digital Electronics- 2 - Question 10

How many AND gates are required for a 1-to-8 multiplexer?

Detailed Solution for Test: Digital Electronics- 2 - Question 10

The number of AND gates required will be equal to the number of outputs in a demultiplexer.

Test: Digital Electronics- 2 - Question 11

The logic circuit shown in figure is :

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 12

In a dual slope ADC if reference voltage is 100 mV and the first integration period is set as 50 msec.

For an input voltage of 120 mV, the second integration (de-integration) period is___ ms


Detailed Solution for Test: Digital Electronics- 2 - Question 12

t = 60 m sec

*Answer can only contain numeric values
Test: Digital Electronics- 2 - Question 13

In a dual slope type digital voltmeter, an unknown signal voltage is integrated our 100 cycles of clock. If the signal has a 50 Hz pick up the maximum clock frequency can be__ kHz


Detailed Solution for Test: Digital Electronics- 2 - Question 13

50 x 100

Test: Digital Electronics- 2 - Question 14

In circuit given if both Transistors have same VT what is the approximate value of highest possible output voltage vout if vh, can range from 0 to VDD, it is assumed that 0 < vT < VDD

Test: Digital Electronics- 2 - Question 15

In the latch circuit shown, the NAND gates have non-zero, but unequal propagation delays. The present input condition is P = Q = 0. If the input condition is changed simultaneously to P = Q = 1, the outputs X and Y are:

Detailed Solution for Test: Digital Electronics- 2 - Question 15

Explanation:
In an SR latch constructed with NAND gates, the outputs X and Y are complementary. When both inputs P and Q are set to 0, both outputs become 1, which is an invalid state for an SR latch. Transitioning both inputs to 1 simultaneously can lead to an indeterminate state due to unequal propagation delays of the NAND gates. This results in the outputs X and Y settling into either X = 1, Y = 0 or X = 0, Y = 1.

Test: Digital Electronics- 2 - Question 16

In the I.C. logic gate shown in figure.

If threshold voltage VBE is o.75 volt and VCE (sat) = 0.2 V, calculate. Value of output voltage

Q. If VA = VB = 4.5 volt

Detailed Solution for Test: Digital Electronics- 2 - Question 16

It is A NAND gate and if VA= VB = 4.5
Then o/p will be logic zero, as both are logic high

SO V0 = VCE, sat = 0•2v

Test: Digital Electronics- 2 - Question 17

For a 3-variable Boolean function F(A, B, C) = Σ(1, 3, 4, 5), what is the simplified Boolean expression for F using a K-map?

Detailed Solution for Test: Digital Electronics- 2 - Question 17

Explanation:

Using a K-map for the given minterms (1, 3, 4, 5), we can group the adjacent cells and obtain the simplified Boolean expression A'B + AB', which represents the minimized sum-of-products form.

Test: Digital Electronics- 2 - Question 18

 

For the output F to be 1 in the logic circuit shown, the input combination should be

Detailed Solution for Test: Digital Electronics- 2 - Question 18

Test: Digital Electronics- 2 - Question 19

For a 2-bit ripple counter made using JK flip-flops, if the clock frequency is 10 kHz, what is the output frequency of the second flip-flop?

Detailed Solution for Test: Digital Electronics- 2 - Question 19

Explanation:

A ripple counter divides the clock frequency by a factor of 2 for each subsequent flip-flop. Therefore, the output frequency of the second flip-flop will be half of the clock frequency, which is 5 kHz.

Test: Digital Electronics- 2 - Question 20

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is

Detailed Solution for Test: Digital Electronics- 2 - Question 20

The minimum number of 2-input NAND gates required to implement a 2-input XOR gate is 4. Here's how:

 


  • An XOR gate outputs true only when inputs differ.

  • Using De Morgan's laws and logic gate properties, XOR can be expressed using NAND gates.

  • Steps to implement XOR using NAND:

    • Create NOT gates for each input: 2 NAND gates

    • Combine inputs with their negations to form AND functionality using NAND gates: 2 more NAND gates

    • Use a final NAND gate to combine these results, achieving XOR: 1 additional NAND gate


    •  

  • Total: 4 NAND gates.


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