Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Test: DRAM Interfaces - Computer Science Engineering (CSE) MCQ

Test: DRAM Interfaces - Computer Science Engineering (CSE) MCQ


Test Description

15 Questions MCQ Test - Test: DRAM Interfaces

Test: DRAM Interfaces for Computer Science Engineering (CSE) 2024 is part of Computer Science Engineering (CSE) preparation. The Test: DRAM Interfaces questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: DRAM Interfaces MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: DRAM Interfaces below.
Solutions of Test: DRAM Interfaces questions in English are available as part of our course for Computer Science Engineering (CSE) & Test: DRAM Interfaces solutions in Hindi for Computer Science Engineering (CSE) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: DRAM Interfaces | 15 questions in 25 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: DRAM Interfaces - Question 1

In which pin does the data appear in the basic DRAM interfacing?

Detailed Solution for Test: DRAM Interfaces - Question 1

Explanation: In the basic DRAM interfacing, the higher order bits asserts the RAS signal and the lower order bits asserts the CAS signal. When the access got expired, the data appears on the dout pin and is latched by the processor.

Test: DRAM Interfaces - Question 2

What is the duration for memory refresh to remain compatible?

Detailed Solution for Test: DRAM Interfaces - Question 2

Explanation: The memory refresh is performed every 15 microseconds in order to remain compatible.

1 Crore+ students have signed up on EduRev. Have you? Download the App
Test: DRAM Interfaces - Question 3

Which interfacing method lowers the speed of the processor?

Detailed Solution for Test: DRAM Interfaces - Question 3

Explanation: The direct method access limits the wait state-free operation which lowers the processor speed.

Test: DRAM Interfaces - Question 4

What is EDO RAM?

Detailed Solution for Test: DRAM Interfaces - Question 4

Explanation: EDO RAM is a special kind of random access memory which can improve the time to read from the memory on faster microprocessors. The example of such a microprocessor is Intel Pentium.

Test: DRAM Interfaces - Question 5

What is RDRAM?

Detailed Solution for Test: DRAM Interfaces - Question 5

Explanation: Rambus DRAM is a synchronous memory developed by Rambus. It can replace SDRAM and is useful in high bandwidth applications.

Test: DRAM Interfaces - Question 6

 Which of the following can transfer up to 1.6 billion bytes per second?

Detailed Solution for Test: DRAM Interfaces - Question 6

Explanation: The Rambus RAM can transfer up to 1.6 billion bytes per second. It possesses RAM controller, a bus which connects the microprocessor and the device, and a random access memory.

Test: DRAM Interfaces - Question 7

Which of the following cycle is larger than the access time?

Detailed Solution for Test: DRAM Interfaces - Question 7

Explanation: The read cycle in the DRAM interfacing is larger than the access time because of the precharge time.

Test: DRAM Interfaces - Question 8

Which mode of operation selects an internal page of memory in the DRAM interfacing?

Detailed Solution for Test: DRAM Interfaces - Question 8

Explanation: In the page mode operation, the row address is provided as normal but the RAS signal is left asserted. This, in turn, selects an internal page within the DRAM memory where any bit of data can be accessed by placing the column address and asserting CAS.

Test: DRAM Interfaces - Question 9

What is the maximum time that the RAS signal can be asserted in the page mode operation?

Detailed Solution for Test: DRAM Interfaces - Question 9

Explanation: The maximum time that the RAS signal can be asserted during the page mode operation is about 10 microseconds. But this is a major disadvantage for page mode operation, that is, the standard PCs have a maximum time of 15 microseconds for the refresh cycle.

Test: DRAM Interfaces - Question 10

Which of the following mode of operation in the DRAM interfacing has a page boundary?

Detailed Solution for Test: DRAM Interfaces - Question 10

Explanation: The page mode operation have memory cycles that exhibit some form of locality, that is, stay within the page boundary which causes page missing when there is an access outside the page boundary and two or more wait states.

Test: DRAM Interfaces - Question 11

Which mode offers the banking of memory in the DRAM interfacing technique?

Detailed Solution for Test: DRAM Interfaces - Question 11

Explanation: The accessing of data outside the page boundary can cause missing of pages in the page mode operation. So a program has to operate for frequently accessing data thereby, increasing the efficiency in the page selection. One such mode is the page interleaving mode in which the memory is divided into different banks, depending on the number of memories installed.

Test: DRAM Interfaces - Question 12

 Which of the following has a fast page mode RAM?

Detailed Solution for Test: DRAM Interfaces - Question 12

Explanation: Extended data out memory is a fast page mode RAM which has a faster cycling process which makes EDO memory a faster page mode access.

Test: DRAM Interfaces - Question 13

 Which mode reduces the need for fast static RAMs?

Detailed Solution for Test: DRAM Interfaces - Question 13

Explanation: The page mode, nibble mode devices can provide data fastly when the new column address is given. In burst mode operation, the processor can fetch more data than it needs and keeps the remaining data in an internal cache for the future use which can reduce the need for fast static RAMs.

Test: DRAM Interfaces - Question 14

Which of the following is also known as hyper page mode enabled DRAM?

Detailed Solution for Test: DRAM Interfaces - Question 14

Explanation: The EDO DRAM is also known as hyper page mode enable DRAM because of the faster page mode operation along with some additional features.

Test: DRAM Interfaces - Question 15

What does BEDO DRAM stand for?

Detailed Solution for Test: DRAM Interfaces - Question 15

Explanation: The burst EDO DRAM is evolved from the EDO DRAM and it can access four memory addresses in one burst. It also supports pipeline stages which allow the page access cycle into two parts.

Information about Test: DRAM Interfaces Page
In this test you can find the Exam questions for Test: DRAM Interfaces solved & explained in the simplest way possible. Besides giving Questions and answers for Test: DRAM Interfaces, EduRev gives you an ample number of Online tests for practice

Top Courses for Computer Science Engineering (CSE)

Download as PDF

Top Courses for Computer Science Engineering (CSE)